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AR# 50228

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1/Vivado 2012.1) - Incorrect Core Functionality when Performance Level is set to 'Extreme' in Gen1/Gen2 Core Configuration

Description

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

When Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 is generated for Gen1/Gen2 speed and the performance level in the GUI is set to Extreme, it results in incorrect core functionality.

Solution

This is a known issue to be fixed in a future release of the core.

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
06/06/2012 - Initial release

Linked Answer Records

Master Answer Records

AR# 50228
Date Created 06/06/2012
Last Updated 07/03/2013
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2012.1
  • ISE Design Suite - 14.1
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)