Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)
The generatedHDL file (inside 'synth' and 'sim' directories in Vivado core generation directory structure) has the *_CAPABILITY_POINTER value set to 'H20 instead of 'H80.
This is a known issue to be fixed in a future revision of the core.
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Revision History
06/04/2012 - Initial release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 47441 | Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for All Versions | N/A | N/A |