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AR# 50299

7 Series FPGAs Transceivers Wizard and Aurora 8B10B/64B66B Cores - Support for GTX Transceivers in Zynq Devices

Description

The 7 Series FPGAs Transceivers Wizard v2.1 and the Aurora 8B10B/64B66B cores in ISE 14.1/Vivado 2012.1 do not support the Zynq device transceivers. This answer record discusses the workaround until this is supported in the ISE 14.2/Vivado 2012.2 version.

Solution

The following table shows all the Zynq device/package combinations with transceivers:
1. XC7Z030 device - FBG484, FBG676, FFG676 packages
2. XC7Z045 device - FBG676, FFG676, FFG900 packages
Package FBG484 FBG676 FFG676 FFG900
Zynq No of GTX Max line rate No of GTX Max line rate No of GTX Max line rate No of GTX Max line rate
XC7Z030 4 6.6 Gb/s 4 6.6 Gb/s 4 12.5 Gb/s
XC7Z045 8 6.6 Gb/s 8 12.5 Gb/s 16 12.5 Gb/s

For GTX transceiver support on these Zynq devices, please follow the following steps to be able to generate core files by invoking similar Kintex-7 devices from the Coregen:

For Zynq XC7Z030 device - All packages:
1. Select a Kintex-7 device with 4 GTX transceivers from CORE Generator (for example,XC7K160T FBG484).
2. Limit the maximum line rate to 6.6 Gb/s if you need the core files for an FBG package, even if the GUI allows for a higher line rate (For Kintex-7 devices the maximum line rate is not dependent on package type and can be up to 12.5 Gb/s for all packages while in Zynq it is limited to 6.6 Gb/s for FBG packages and is 12.5 Gb/s for FFG packages).
3. Open the UCF/XDC file and change the constraints and pin locations based on the inputs from FPGA editor.
For Zynq XC7Z045 device FBG676 & FFG676 packages:
1.Select a Kintex-7 device with 8 GTX transceivers from CORE Generator (for example,XC7K325T FBG676).
2. Limit the maximum line rate to 6.6 Gb/s if you need the core files for an FBG package even if the GUI allows for a higher line rate ( For Kintex-7 devices the maximum line rate is not dependent on package type and can be up to 12.5 Gb/s for all packages while in Zynq it is limited to 6.6 Gb/s for FBG packages and is 12.5 Gb/s for FFG packages).
3. Open the UCF/XDC file and change the constraints and pin locations based on the inputs from FPGA editor.
For Zynq XC7Z045 device FFG900 package:
1. Select a Kintex-7 device with 16 GTX transceivers from CORE Generator(for example,XC7K325T FFG900).
2. Open the UCF/XDC file and change the constraints and pin locations based on the inputs from FPGA editor.
Note: If the implementation scripts generated with the example design are used, then replace the Kintex-7 device selected above with the correct Zynq device and package in the "implement.sh", "implement.bat", "planahead_rdn.tcl", "xst.scr" files.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
41613 7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List N/A N/A
AR# 50299
Date Created 06/08/2012
Last Updated 01/21/2013
Status Active
Type General Article
Devices
  • Zynq-7000
IP
  • 7 Series FPGAs Transceivers Wizard
  • Aurora 64B/66B
  • Aurora 8B/10B