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AR# 50312

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 (ISE 14.1 / Vivado 2012.1) - The Core does not Transmit Memory Read TLPs Upstream

Description

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

When trying to send Memory Read TLPs to the link partner, the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.1 core does not transmit those TLPs even though the TLPs are correctly presented to the core by the backend endpoint user application. There is no issue with completion TLPs.

Solution

This is a known issue to be fixed in a future release of the core. As a workaround, set the "AXISTEN_IF_RQ_PARITY_CHK" parameter to 'FALSE'. This parameter is set to 'TRUE' by default. This parameter can be found in pcie_3_0_7vx.v file in 'source' directory.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
06/06/2012 - Initial release

Linked Answer Records

Master Answer Records

AR# 50312
Date Created 06/05/2012
Last Updated 06/06/2012
Status Active
Type Known Issues
Tools
  • Vivado - 2012.1
  • ISE Design Suite - 14.1