We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
This is an expected behavior and is seen for all devices.
When the .ucf file is not provided/empty, the .pcf file is empty.
In this case the SDF file generated does not need to be timing aware and you can only perform a default analysis while running timing simulation using the MAX values (worst case) which are only present in the file.
These are the worst delays which would be used by the tool while running simulation.
Was this Answer Record helpful?
CPLD Device Families
FPGA Device Families
ISE Design Suite