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AR# 50356

LogiCORE IP Ten Gigabit Ethernet PCS/PMA (10GBASE-KR) v2.3 - training_rddata is delayed one clock cycle relative to training_rdact when reading the 802.3 registers

Description

When using the 10GBASE-KR training interface, training_rddata is delayed one clock cycle relative to training_rdact when reading the 802.3 registers.

This is not an issue when reading the DRP registers.

The problem can be seen in simulation.

Solution

The following work-arounds can be used:

  • Use the MDIO or status vector.

A fix for this issue is available in the below v2.3 rev2 patch.

The v2.3 rev2 patch also includes the fix from the v2.3 rev1 patch, see (Xilinx Answer 47943) for more details. 

The patch will be included in the v2.4 release of the core.

Installation/Use: This patch is for use with ISE 14.1 and Vivado 2012.1 design tools.

Install the patch below by extracting the contents of the ".zip" archive to the root directory of the XILINX (Xilinx ISE installation). 

Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.

For further information on finding the Xilinx install and using environment variable, see (Xilinx Answer 11630).

NOTE: You might be required to have a system administrator to install the patch if you do not have write permissions to the Xilinx Install directory.

Attachments

Associated Attachments

Name File Size File Type
ar50356_ten_gig_eth_pcs_pma_v2_3_rev2.zip 49 KB ZIP
AR# 50356
Date Created 06/07/2012
Last Updated 10/22/2014
Status Active
Type General Article
IP
  • 10 Gigabit Ethernet PCS-PMA with FEC/Auto-Negotiation for backplanes (10GBASE-KR)