We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50359

Vivado IP Flows - How do I generate the structural simulation model for an IP core in a Vivado project?


When generating an IP core from the IP Catalog within a Vivado project, it does not appear to be possible to choose to generate structural simulation models as opposed to the default behavioral simulation models.

How do you switch to structural models?


There are currently three options on how to achieve this as follows:

  • Create a separate project for the IP, synthesize and use write_verilog or write_vhdl to get the structural netlist for the core. You can use the Manage IP flow in the Vivado tool to generate the separate IP core project.
  • Another option is to set the IP core as the top level in the overall project, synthesize it, and write the verilog or VHDL file and add it to the project; this way, you do not need to create a separate project or copy the original IP.
  • You can also use CORE Generator standalone with the CORE Generator project settings set to structural simulation model, and then import the sources into the Vivado tool.

Linked Answer Records

Associated Answer Records

AR# 50359
Date Created 06/07/2012
Last Updated 02/18/2016
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite
  • FIFO