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AR# 504

SYNPLIFY: How to prevent the grouping of ports into arrays in the output EDIF netlist using the syn_noarrayports attribute?

Description

Keywords: Synplify, Verilog, VHDL, syn_noarrayports

Urgency: Standard

General Description:
How to prevent the grouping of ports into arrays in the output
EDIF netlist using the syn_noarrayports attribute?

The syn_noarrayports attribute specifies that the ports on a
design unit should be left as scalars and not grouped into an
array (bus) notation during synthesis. This should be applied
to the top level entity or module.

See also (Xilinx Solution 2649) on information on modifying the
bus-notation in an EDIF generated netlist.

Solution

1

VHDL
----

library synplify, ieee;
use synplify.attributes.all;
use ieee.std_logic_1164.all;

entity TOP is
port (A, B : in std_logic_vector(7 downto 0);
CIN : in std_logic;
SUM : out std_logic_vector(7 downto 0);
COUT : out std_logic);
attribute syn_noarrayports of TOP : entity is true;

end TOP;

2

Verilog
-----

module TOP (A, B, CIN, SUM, COUT)
/* synthesis syn_noarrayports=1 */;

AR# 504
Date Created 09/20/1995
Last Updated 04/24/2007
Status Archive
Type General Article