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AR# 50446

LogiCORE IP 1000BASE-X PCS/PMA or SGMII v11.3, Artix-7 - Missing TXOUTCLK BUFG

Description

This issue occurs with v11.3 of the 1000BASE-X PCS/PMA or SGMII core when targeting Artix FPGA 200t silicon (does not apply when targeting Artix FPGA 100t silicon).

The following error message occurs when implementing the example design:

The ucf constraint txoutclk is not found.


After I work around the first one, I get the following error: 

ERROR:PhysDesignRules:2369 - Issue with pin connections and/or configuration on block:<mmcm_adv_inst>:<MMCME2_ADV_MMCME2_ADV>. The MMCME2_ADV with CLKINSEL tied High requires the CLKIN1 pin to be active.
ERROR:Pack:1642 - Errors in physical DRC.


The MMCM_ADV instantiation is missing the CLKIN1 port.

Solution

If targeting the Artix FPGA 200T silicon (regardless of core configuration), the example design top-level seems to be missing the TXOUTCLK BUFG and all of its connection to the MMCM.

To fix this issue, add the following codes in the example_design\gig_eth_pcs_pma_v11_3_example_design.v:

1. On the wire declaration, add:

wire txoutclk_bufg; // txoutclk from GT transceiver routed onto global routing.


2. On the body of the module, add the bufg:

// Route txoutclk input through a BUFG
BUFG bufg_txoutclk (
.I (txoutclk),
.O (txoutclk_bufg)
);


3. On the MMCM instantiation, add the following in the //input clock control section:

.CLKIN1 (txoutclk_bufg),

Revision History
6/14/2012 - Initial release

AR# 50446
Date Created 07/10/2012
Last Updated 10/24/2014
Status Active
Type Known Issues
Devices
  • Artix-7
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII