The calibration algorithm and hard block settings for all interfaces have been updated in MIG 7 Series v1.6. All users must upgrade to MIG 7 series v1.6 as the previous calibration algorithm and hard block settings can exhibit calibration failures and data corruption on reads.
Note: MIG 7 Series v1.6 is not production status IP. Users must upgrade to v1.7 or higher. Please upgrade IP and see (Xilinx Answer 53420).
This Design Advisory details the changes made to the calibration algorithm in MIG 7 Series v1.6.
Updated Phaser_OUT Circular Buffer Settings (All Interfaces):
Description: Changes to the Phaser_OUT circular buffer initialization have been implemented to ensure, across FPGA process variation, the Phaser_OUT outputs are phase aligned.
Potential Failure Mode: Without the updated Phaser_OUT Cicular Buffer settings, some devices may exhibit Write Leveling or Write Calibration Failures due to misaligned Phaser_OUT outputs. For example, ddr_can_n and ddr_addr are misaligned by one clock cycle.
Fix: Updated Phaser_OUT Circular Buffer initial values.
Updated Phaser_IN and DQS IOB Configuration (DDR3 and DDR2 Only):
Description: Changes to the configuration of the Phaser_IN block have been implemented to ensure reliable DQS preamble detection across all possible component (FPGA and DRAM) variations.
Potential Failure Mode: Without the Phaser_IN block configuration changes, some devices may exhibit data corruption on reads at high data rates shortly after operation begins.
Fix: Updated UCF and rtl Phaser_IN and I/O configuration.