We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50557

Kintex-7 FPGA Connectivity Kit TRD - 10G PCS-PMA core modifications


10G PCS-PMA core has been custom modified for use in the Kintex-7 FPGA Connectivity Kit TRD.


Modifications to the 10G PCS-PMA core used in the Kintex-7 FPGA Connectivity Kit TRD include:

- To use two instances of the IP, the GT wrappers for two GT sharing a quad and not sharing a quad have been generated separately

- For use of 312.5 MHz clock provided by FMC, the parameter QPLL_REFCLK_DIV is changed to 2 in files:
'ip_cores/xphy_gt_wrapper/gtwizard_10gbaser_same_quad.v' and

- MMCM is used to derive 156.25 MHz for XGEMAC

- In addition to (Xilinx Answer 45360) suggested changes, the following attributes are also updated:
RX_CLKMUX_PD = 1 (xphy_gt_wrapper/gtwizard_*_quad_gt.v)
TX_CLKMUX_PD = 1 (xphy_gt_wrapper/gtwizard_*_quad_gt.v)

Linked Answer Records

Master Answer Records

AR# 50557
Date Created 06/28/2012
Last Updated 11/28/2012
Status Active
Type General Article
Boards & Kits
  • Kintex-7 FPGA Connectivity Kit