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AR# 5057

4.2i Foundation Timing Simulator - Metastable operation not accurately simulated (undefined state persists)


Keywords: Timing, Simulator, metastable, Foundation, metastability, undefined, setup, hold

Urgency: Standard

General Description:
When a metastable operation occurs in timing simulation in the Foundation simulator, the simulator does not go stable until either a clear, a preset, or the next clock cycle is encountered.


If a setup or hold time parameter is violated in simulation, the FF/latch output will not be defined.

If an actual device register goes into a metastable state, it will probably recover well within 1 ns and the design process will continue. This process is outlined in the Xilinx Application Note "Metastable Recovery" (Xilinx XAPP094).
AR# 5057
Date Created 11/17/1998
Last Updated 08/12/2003
Status Archive
Type General Article