AR# 50572 Zynq-7000 Example Design - Interrupt handling of PL generated interrupt
Description
This example design implements a timer in PL, and the interrupt of the timer will ring theCPU by GIC IRQ.
Note: An Example Design is an answer record that providestechnical tips to test a specific functionalityon Zynq-7000. Atip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools. It isup to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design tofulfill his needs. Limited support is provided by Xilinx on these Example Designs.
Solution
| Implementation Details | |||
|---|---|---|---|
| Design Type | PS and PL | ||
| SW Type | Standalone | ||
| CPUs | Single CPU | ||
| PS Features | GIC, UART1 | ||
| PL Cores | AXI TIMER | ||
| Boards/Tools | ZC702 | ||
| Xilinx Tools Version | EDK 14.1 | ||
| Other details | USB cable II or Digilent cable, mini cable, PS configuration is ZC702template. | ||
| Address Map | |||
| Base Address | Size | Bus Interface | |
| AXI TIMER | 0x42800000 | 64K | S_AXI |
Step by Step Instructions
1. Import the archived design into XPS and export to SDK with bitstream.
2. In SDK, create a Hello World example.
3. Replace helloworld.c with the snippet of C code. Be careful of the interrupt ID, it counts from the high end of the PL interrupt ID number.
XPAR_FABRIC_AXI_TIMER_0_INTERRUPT_INTR is 91 in xparameters.h.
4. Program the PL using the bitstream generated by XPS.
5. Setup the terminal to watch Uart output.
6. Run the application.
Expected Results
Interrupt information will print in the terminal repeatedly.
Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 51779 | Zynq-7000 AP SoC Example Designs | N/A | N/A |
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