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AR# 50586

Design Advisory for LogiCORE IP Video Deinterlacer v2.00.a and v3.00.a - Why do I always receive zeros back when reading from the Video Deinterlacer Registers?

Description

Why do I always receive zeros back when reading from the Video Deinterlacer registers?

Solution

This is a known issue with the Video Deinterlacer v2.00.a and v3.00.a.

The Video Deinterlacer v2.00.a and v3.00.a require that the m_axi_clk to be present even if the user has unselected the Include Motion Algorithm (C_MOTION = 0).
Also, the m_axi_aresetn is required to make sure that the core completely resets, and should be connected to the same signal as the s_axi_aresetn on the AXI4-Lite control interface.

This issue will be resolved in a future release of the Video Deinterlacer.

In the meantime, you can perform the following to work around the problem:

CORE Generator

  • The user must connect up the m_axi_aclk to the same clock as the s_axi_aclk.
  • The user connect up the m_axi_aresetn to the same signal as the s_axi_aresetn.

EDK

  • All users are encouraged to download and the patch (pick the correct one for your version of software) located at the end of this answer record, extract the ZIP to to your $XILIND_EDK directory, and restart XPS.
    • For the Video Deinterlacer v2.00.a in 14.1 and 14.2 EDK, it is recommended that all users download and install the patch at the end of this answer record.
    • For the Video Deinterlacer v2.00.a in 14.3 and later, the patch has been included and users can skip to the section below that describes the connections needed in EDK.
    • For the Video Deinterlacer v3.00.a in 14.3 and later, the patch has been included and users can skip to the section below that describes the connections needed in EDK.
  • The user should then be able to connect the m_axi_aclk signal to the same clock as s_axi_aclk via the ports selection tab in XPS.
  • The user must connect up m_axi_aresetn to the same signal as s_axi_aresetn.

EDK Note:

  • In order to make the proper connection, you might need to make the Net Column visible in the Ports listing:
    • This can be done by right-clicking on the connected Port option, and then select Nets.
    • Then, right-click on the m_axi_aresetn signal and select New Connection. This will then make a connection in the MHS file.
      PORT m_axi_aresetn = v_deinterlacer_0_m_axi_aresetn

For a detailed list of LogiCORE IP Video Deinterlacer Release Notes and Known Issues, see (Xilinx Answer 41969).

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AR# 50586
Date Created 06/26/2012
Last Updated 05/17/2013
Status Active
Type Design Advisory
IP
  • Video Deinterlacer