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AR# 50633

AXI Bridge for PCI Express - Root Port Implementation does byte swap to the completion packet for a configuration read issued to an Endpoint device

Description

Version Found: v1.03a, v1.04a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)

When operating in Root Port mode, if configuration read packets were sent to an Endpoint device, the returned completion from that configuration read will be byte-reversed by the AXI_PCIe bridge of the Root Controller.

Solution

The example Root Controller driver provided by Xilinx will automatically handle this situation. Users who write their own driver should be aware of this issue and make sure that their driver handles this issue correctly.

This information will be added into the next release of the documentation.

Revision History
07/25/2012 - Initial release

Note: The "Version Found" column lists the version in which the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 50633
Date Created 07/24/2012
Last Updated 01/21/2013
Status Active
Type Known Issues
Tools
  • EDK - 14.1
  • EDK - 14.2
IP
  • AXI PCI Express (PCIe)