UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50656

13.4 FIFO Generator v8.4: FIFO Generator Design with AXI-Stream Packet FIFO configuration fails in simulation with deadlock condition

Description

My design fails in simulation in a deadlock condition when the FIFO Generator is used in AXI-Stream Packet FIFO configuration.

During simulation both M_AXIS_TVALID and S_AXIS_TREADY are de-asserted at the same time which causes the deadlock situation.

Solution

This is a known design limitation with FIFO Generator v8.4 and beyond, and occurs when the FIFO depth is less than or equal to the packet size.

To work around this, the FIFO depth should be at least twice the maximum packet size for AXI-Stream Packet FIFO.

AR# 50656
Date Created 07/03/2012
Last Updated 09/10/2014
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • ISE Design Suite - 13.4
IP
  • FIFO Generator