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AR# 50698 MIG 7 Series DDR3/DDR2 - Some configurations fail to meet timing due to logic not being placed properly

Description

Version Found: v1.5
Version Resolved and other Known Issues: See (Xilinx Answer 45195).

In some MIG 7 seriesDDR3/DDR2 configurations, some logic is not being placed within the correct clock region, which causes excessive net delay going to some of the hard blocks (ex. OUT_FIFO).

Solution

This is an issue related to the placement algorithm and not to the MIG design itself. To work around the issue, the user can manually set AREA_GROUP constraints to force the placer to place the logic within the same clock region, or the following environment variable can be set:

PL_DLYPENALTY=1500

For instructions on how to setup an environment variable please refer to (Xilinx Answer 11630).

Revision History
07/25/2012 - Initial release of AR

Actions

AR# 50698
Date Created 07/11/2012
Last Updated 01/16/2013
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Artix-7
  • Virtex-7
IP
  • MIG 7 Series
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