Xilinx recommends upgrading to the latest version of MIG to work around the issue, but users can also work around this by creating a custom memory part using a different single rank part selected as the base part, and then manually entering the timing specifications for theMT9JSF25672PZ.
Users can also work around this by modifying the following parameters:
CS_WIDTH = 1
nCS_PER_RANK = 1
PHY_0_BITLANES= 48'h000_000_000_000,(value depends on pinout andCS placement, refer to
UG586for details)
PHY_1_BITLANES= 48'h000_000_000_000,(value depends on pinout andCS placement, refer to
UG586for details)
PHY_2_BITLANES = 48'h000_000_000_000,(value depends on pinout andCS placement, refer to
UG586for details)
CS_MAP = 120'h000_000_000_000_000_000_000_000_000_0XX, (value depends on CS placement, refer to
UG586 for details)
Revision History07/25/2012 - Initial release of AR