Version Found: v1.6 Version Resolved and other Known Issues: See (Xilinx Answer 45195).
The MIG 7 Series VHDL designs contain mixed VHDL and Verilog modules which cause a problem for ISIM and Vivado Simulator when attempting to pass down parameters across modules.
Solution
You might notice ISIM/Vivado Simulator exiting during compilation with erroneous error messages. This has been fixed for Vivado Simulator only.