This Release Note is for the XADC Wizard v2.1 released in ISE Design Suite 14.2, and the XADC Wizard v2.2 released in Vivado 2012.2 tools.
It contain the following information:
The XADC Wizard v2.1 and v2.2 supports the 7 Series and Zynq devices. You can use the Wizard to customize the I/O Ports usage, the User Alarms and Thresholds, and the Channel Sequencer.
New Features in v2.1 and v2.2
There are no new features in v2.1 and v2.2.
Bug Fixes in v2.1 and v2.2
There are no bug fixes in v2.1 and v2.2.
Known Issues v2.1
There are currently no known issues for the v2.1 XADC Wizard.
Known Issues v2.2
In the v2.2 XADC wizard there two known issues.
1) The Vivado tool might issue a warning on the setup time while running timing simulation of XADC Wizard example designs.
This is due to the routing delay on DADDR and RESET input with reset to the clock.
2) The Vivado tool issues a critical warning similar to the following when implementing a Verilog project due to the instance name INST being in upper case:
To work around the issue, change INST to inst in the <component_name>.v.
7/25/2012 - Initial Release