Version Found: v1.5
Version Resolved and other Known Issues: See
(Xilinx Answer 45195).
Data mismatch errors can occur when simulating the MIG 7 Series RLDRAM II design when set to BL=8. A case can occur where the User Interface (UI) FIFO goes full before a command is written but the Traffic Generator (TG) continues on and sends the next command. Since the previous command is not written properly the compare logic detects a read data mismatch error later on.