We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50782

14.1 - Graphical Design View GUI Shows Incorrect Clock Value


When using XPS 14.1, the clock values in the Graphical Design View are incorrect. 

For a SP605, the AXI_ACLK signal should be 62.5MHz for the PCIe IP core but the Design View shows a value of 125MHz.


This issue only occurs when using the MMCM instance within the PCIe core as the system clock.  

When a separate Clock Generator core is included in the design this error does not occur.

The AXI_ACLK does have a value of 62.5MHz.  

The GUI displays it as 125MHz as this is what all devices other than the Spartan-6 would be (Per DS820).

AR# 50782
Date Created 07/11/2012
Last Updated 09/15/2014
Status Active
Type General Article
  • EDK
  • EDK - 14
  • EDK - 14.1
  • PCI-Express (PCIe)