We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 50788

LogiCORE Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v2.3 - Updates needed to example design UCF


I am using the LogiCORE Ten Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v2.3 example design .ucf file for 7 series.

Some of the constraints are not passed through the MMCM and this results in unconstrained paths.  

This does not apply if using the constraints in Vivado Design Suite.


Attached below is an updated .ucf constraint file to resolve the issue.  

Constraints with #New above them are new constraints and Constraints with #Updated have been updated.  

This issue is resolved in the next release of the core: v2.4 in the ISE 14.2/2012.2 release.


Associated Attachments

Name File Size File Type
ten_gig_eth_pcs_pma_v2_3_baser_example_design.ucf 5 KB UCF
AR# 50788
Date Created 07/12/2012
Last Updated 10/22/2014
Status Active
Type General Article
  • Ten Gigabit Ethernet PCS/PMA
  • 10 Gigabit Ethernet PCS-PMA with FEC/Auto-Negotiation for backplanes (10GBASE-KR)