Timing failures might occur in the XAUI core Example Design if targeting 7 series FPGAs.
To work around this issue, the core can be constrained to be placed close to the selected GTs.
In the XDC file, one of the following area groups can be used:
A. Create a slice range area group:(Where SLICE_XnnnYnnn:SLICE_XnnnYnnn are the appropriate ranges to place the core adjacent to the GT).
B. If a clock region is desired instead of a slice range, the following could be used:(Where XnYn are the appropriate numbers for the clock region neighboring the GT).