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AR# 50800

2012.2 Vivado - INIT attribute viewed in the Vivado Integrated Design Environment are displayed in Verilog format regardless of project settings


Both PlanAhead and Vivado INIT attribute values are displayed in Verilog format regardless of whether VHDL or Verilog  is chosen in the project settings .

For example, the Flip-Flop INIT value is shown in the Netlist Instance Attributes panel as either 1'b0 or 1'b1.


The LUT INIT attribute value was designed to be displayed in Verilog format and has no connection to the selected HDL language of the project.

Due to customer feedback, in Vivado 2012.3, the format of the INIT value has been changed to a more generic format that will not be associated with a specific HDL language.

AR# 50800
Date Created 10/17/2012
Last Updated 06/05/2014
Status Active
Type General Article
  • Vivado Design Suite
  • PlanAhead