This example design allocates 4K of block RAM attached to the CPU via M_AXI_GP0. The same block RAM is also accessible by the CDMA.
The CPU initializes the block RAM. The CDMA in simple mode is transferring data from the block RAM to the OCM via ACP port. The transfer is cache coherent and when the transfer is complete, the CPU sees the updated OCM without invalidating or flushing the cache.
Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000. A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools. It is up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfil their needs. Limited support is provided by Xilinx on these Example Designs.
Please see the table below:
|Design Type||PS and PL|
|CPUs||Single CPU @ 667MHz|
|PS Features||MMU, OCM|
|PL Cores||BRAM, CDMA|
|Xilinx Tools Version||Vivado 2015.1|
|Other details||FCLK @ 50MHz|
Archived Vivado project.
|hello_axi_cdma.c||Snippet of code.|
On the Terminal, at the end of the test, the destination memory should match the source memory.
The CPU can see the data transferred by the CDMA without any particular software implemented.