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AR# 50827

7 Series FPGAs Transceiver Wizard v2.2 - Known Issues and Release Notes

Description

This answer record contains the Known Issues and Release Notes for the 7 series FPGAs Transceiver Wizard v2.2, released with the ISE 14.2 and Vivado 2012.2 design tools.

Solution

1. INTRODUCTION

This file contains the change log for all released versions of the Xilinx LogiCORE IP core 7 series FPGAs Transceivers Wizard.

For the latest core updates, see the product page at:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/7-series_fpga_transceivers_wizard.html

For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements, see:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm


2. DEVICE SUPPORT

  2.1. ISE DESIGN SUITE

    The following device families are supported by the core for this release:

    All 7 series devices (excluding Zynq-7000)

  2.2. VIVADO DESIGN SUITE

    All 7 series devices (excluding Zynq-7000)

3. NEW FEATURE HISTORY

  3.1 ISE Design Suite

    v2.2  
    - Support for GTZ Transceiver
    - Support for Production Silicon for GTX
    - Updated settings for Initial ES for GTH 
    - Support for PCIE Gen1/Gen2 protocol for GTP Transceiver 
    - Enhanced Example Design for GTP
    - New Protocol Templates added for GTX - JESD204 
    - New Protocol Templates added for GTH - Aurora 8B/10B 
    - New Protocol Templates added for GTP - SRIO Gen1/Gen2

    v2.1
    - Support for GTP Transceiver
    - Support for Initial ES for GTH
    - Updated settings for General ES for GTX
    - Support for PCIE Gen1/Gen2 protocol for GTH Transceiver
    - Enhanced Example Design for GTX and GTH

    v1.6 
    - Support for GTH Transceiver
    - Support for General ES for GTX
    - Support for PCIE Gen1/Gen2 protocol for GTX Transceiver

    v1.5
    - Support for Initial ES for GTX 

  3.2 Vivado Design Suite

    v2.2  
    - Support for GTZ Transceiver
    - Support for Production Silicon for GTX
    - Updated settings for Initial ES for GTH 
    - Support for PCIE Gen1/Gen2 protocol for GTP Transceiver 
    - Enhanced Example Design for GTP

    v2.1
    - Support for GTP Transceiver
    - Support for Initial ES for GTH
    - Updated settings for General ES for GTX
    - Support for PCIE Gen1/Gen2 protocol for GTH Transceiver
    - Enhanced Example Design for GTX and GTH

    v1.5
    - Support for Initial ES for GTX, including XC7V2000T

4. RESOLVED ISSUES 

  4.1 ISE Design Suite

    The following issues are resolved in the indicated IP versions:

    v2.2
      - Added the component name as a prefix to the module name for all modules
      - CR 665217 
      - 500ns wait time is needed after configuration to assert resets to the GTs
      - CR 665581
      - Updated Frame Gen/ Frame Check Logic for 64B/66B Encoding
      - CR 657496 

  4.2 Vivado Design Suite

    The following issues are resolved in the indicated IP versions:

    v2.2

      - Added the component name as a prefix to the module name for all modules 
      - CR 665217 
      - 500 ns wait time is needed after configuration to assert resets to the GTs
      - CR 665581
      - Updated Frame Gen/ Frame Check Logic for 64B/66B Encoding
      - CR 657496

5. KNOWN ISSUES AND LIMITATIONS

  - This version of the Wizard is NOT native Vivado compatible. Hence Upgrade from earlier versions of the IP is not supported in Vivado. To upgrade from v1.5, v1.6 or v2.1 versions, users can use the Generator tool.
  - Timing Simulation is not supported for Artix-7 FPGA
  - A GTP wrapper cannot be implemented on Hardware due to the issue given in CR 665415
  - Some GTP designs will error out with the message: [Drc 23-20] Rule violation (RTSTAT-6) Partial conflict due to the issue given in CR 667140
  - Simulation failure seen for GTX case when Internal Sequence Counter is used for 64B66B gearbox. The CR # is 668646
  - Implementation of PCI Gen1/Gen2 wrappers generated for GTP transceivers is not supported
  - The Wizard generates Verilog wrappers for GTZ. VHDL is not supported.
  - For GTZ designs, the Wizard supports line rates and reference clocks shown in the GUI. No other values are tested or validated in hardware.
  - It is recommended that the Beachfront module generated for GTZ designs should NOT be modified by the user. Any edits made by the user might lead to unexpected results.
  - Known issues seen during implementation of GTZ designs generated using Start from Scratch template are captured in CRs 668228 and 668293
  - Please note that Vivado flow should be used for implementation of all SSIT devices
  - Please note that the protocol templates provided by the Wizard are not characterized on hardware.
  - For information on GTX Initial ES Settings, refer to (Xilinx Answer 43244).
  - For information on GTH Initial ES Settings, refer to (Xilinx Answer 47128).
  - For information on GTX General ES Settings, refer to (Xilinx Answer 45360).
  - For a comprehensive listing of known issues for this core, please see the IP Release Notes Guide (XTP025).      

6. TECHNICAL SUPPORT AND FEEDBACK

To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product. Feedback on this IP core can also be submitted under the "Leave Feedback" menu item in the Vivado or PlanAhead tools. Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

7. CORE RELEASE HISTORY

Date        By            Version      Description
================================================================================
07/25/2012  Xilinx, Inc.  2.2          ISE 14.2 and Vivado 2012.2.
04/24/2012  Xilinx, Inc.  2.1          ISE 14.1 and Vivado 2012.1; Defense Grade 7 Series and Zynq devices, Automotive Zynq devices.
01/19/2012  Xilinx, Inc.  1.6          ISE 13.4: Minor feature enhancements, completely backward-compatible.
08/19/2011  Xilinx, Inc.  1.5          ISE 13.3
06/22/2011  Xilinx, Inc.  1.4          ISE 13.2: CORE Generator tool flow Support
03/01/2011  Xilinx, Inc.  1.3          Initial release
================================================================================

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
41613 7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List N/A N/A
AR# 50827
Date Created 07/13/2012
Last Updated 11/11/2014
Status Active
Type Release Notes
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • 7 Series FPGAs Transceivers Wizard