Version Found: v1.6
Version Resolved and other Known Issues: See (Xilinx Answer 40469)
Simulation of the Root Port configuration of 7 Series Integrated Block for PCI Express v1.6 is supported for Verilog only.
VHDL support is available only on MTI.
|Cadence Incisive Enterprise Simulator (IES)
|Synopsys VCS and VCS MX||Verilog|
|Mentor Graphics ModelSim (MTI)||Verilog/VHDL|
This is a known issue to be fixed in a future release of the core.
NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
07/25/2012 - Initial release