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AR# 50835

7 Series Integrated Block for PCI Express v1.6 (ISE 14.2/Vivado 2012.2) - VHDL simulation support for Root Port Configuration


Version Found: v1.6
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

Simulation of the Root Port configuration of 7 Series Integrated Block for PCI Express v1.6 is supported for Verilog only.

VHDL support is available only on MTI.

Simulators Language Support
Cadence Incisive Enterprise Simulator (IES)
Synopsys VCS and VCS MX Verilog
Mentor Graphics ModelSim (MTI) Verilog/VHDL
XSIM (Vivado) Verilog


This is a known issue to be fixed in a future release of the core.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
07/25/2012 - Initial release

AR# 50835
Date Created 07/23/2012
Last Updated 02/25/2013
Status Active
Type Known Issues
  • ISE Design Suite - 14.2
  • Vivado - 2012.2
  • 7 Series Integrated Block for PCI Express (PCIe)