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AR# 50837 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.2 (ISE 14.2/Vivado 2012.2) - Some features in Endpoint Configuration not verified

Description

Version Found: v1.2
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

Following are some features that are included in the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.2 Endpoint Configuration but have not been verified yet.

  • Message Transaction and Error Packet Generation from Testbench
  • Generation of Upstream Memory Request which are initiated by writing Specified values into Expansion ROM registers

Solution

This is a known issue to be fixed in a future release of the core.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
07/25/2012 - Initial release

Actions

AR# 50837
Date Created 07/23/2012
Last Updated 07/23/2012
Status Active
Type Known Issues
Tools
  • ISE Design Suite - 14.2
  • Vivado - 2012.2
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
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