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AR# 50864

LogiCORE IP Floating Point Operator (FPO) v5.0 - Why do I see an error in simulation when using the example test bench in 14.2?


Why do I see an error in simulation when using the example test bench in the 14.2 tools?

The behavioral model wrapper for Floating Point Operator v5.0 fails to compile for combinatorial core configurations.

Example ModelSim error message:

Error: proj/floating_point_v5_0_inst.vhd(113): (vcom-1130) Port "CLK" of entity "floating_point_v5_0" is not in the component being instantiated.


This is a known issue with zero latency core configurations. 

To work around this issue, use the structural VHDL simulation model for the core. 

For details of how to select this option, see the CORE Generator documentation.

An alternative work-around is to modify the behavioral model wrapper to add a dummy CLK port tied Low. 

In the component declaration in the wrapper file, add the following line:

clk : in std_logic := '0';

For a detailed list of LogiCORE Floating Point Operator Release Notes and Known Issues, see (Xilinx Answer 29598).

AR# 50864
Date 12/18/2014
Status Active
Type General Article
  • Floating Point Operators
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