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AR# 50880

LogiCORE IP Initiator, Target v4.17 for PCI - Timing error with slack violation for IRDY_N, on Artix-7 devices


When implementing the LogiCORE IP Initiator, Target v4.17 for PCI core on Artix-7 devices, the design runs into the following timing error:

Timing constraint: TIMEGRP "CTL_BUS" OFFSET = IN 7 ns VALID 7 ns BEFORE COMP
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 153 paths analyzed, 95 endpoints analyzed, 2 failing endpoints
 2 timing errors detected. (2 setup errors, 0 hold errors)
 Minimum allowable offset is   7.005ns.
Slack:                              -0.005ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:                         IRDY_N (PAD)
  Destination:                  XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/PCI_AD/XPCI_ADO5 (FF)
  Destination Clock:        CLK rising at 0.000ns
  Requirement:               7.000ns
  Data Path Delay:         12.000ns (Levels of Logic = 4)
  Clock Path Delay:        5.020ns (Levels of Logic = 2)
  Clock Uncertainty:       0.025ns

  Clock Uncertainty:                0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):        0.000ns
    Discrete Jitter (DJ):           0.000ns
    Phase Error (PE):             0.000ns

  Maximum Data Path at Slow Process Corner: IRDY_N to XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/PCI_AD/XPCI_ADO5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    M22.I                Tiopi                 2.129   IRDY_N
    ILOGIC_X0Y119.D      net (fanout=1)        0.000   XPCI_WRAP/IRDYI
    ILOGIC_X0Y119.O      Tidi                  5.701   XPCI_WRAP/IRDYF
    SLICE_X0Y119.D6      net (fanout=13)       0.887   XPCI_WRAP/IRDYF
    SLICE_X0Y119.D       Tilo                  0.124   XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/OUT_CE/PAR_CE
    SLICE_X0Y119.C5      net (fanout=1)        0.278   XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/N14
    SLICE_X0Y119.C       Tilo                  0.124   XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/OUT_CE/PAR_CE
    OLOGIC_X0Y55.OCE     net (fanout=36)       2.280   XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/PCI_CE
    OLOGIC_X0Y55.CLK     Tooceck               0.477   XPCI_WRAP/ADO<5>
    -------------------------------------------------  ---------------------------
    Total                                     12.000ns (8.555ns logic, 3.445ns route)
                                                       (71.3% logic, 28.7% route)

  Minimum Clock Path at Slow Process Corner: PCLK to XPCI_WRAP/XPCI_CORE/U0/xst_pci/pci32_inst/PCI_LC_I/PCI_AD/XPCI_ADO5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    J19.I                Tiopi                 1.961   PCLK
    BUFGCTRL_X0Y31.I0    net (fanout=1)        1.492   XPCI_WRAP/CLK_NUB
    BUFGCTRL_X0Y31.O     Tbccko_O              0.105   XPC


This is a known issue and is resolved in version 4.18 of the core. 

This issue can be worked around by reducing the fabric delay by two taps on the failing nets. 

In the above example, it would require going into the UCF and reducing the IRDY (source pin) fabric delay by two taps.

Revision History:
07/25/2012 - Initial Release
09/18/2014 - This issue has been fixed. For more information see (Xilinx Answer 52452)

AR# 50880
Date Created 07/24/2012
Last Updated 10/16/2014
Status Active
Type Known Issues
  • Artix-7
  • ISE Design Suite - 14.2
  • Vivado Design Suite - 2012.2
  • 32-bit Initiator/Target for PCI
  • 64-bit Initiator/Target for PCI