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AR# 50883

LogiCORE IP Serial RapidIO Gen2 v1.5 (ISE 14.2) - Implementation might fail with slack violation timing error


If implementing the LogiCORE IP Serial RapidIO Gen2 v1.5 core on ISE Design Suite 14.2 in one of the following configurations, it can result in timing error with slack violation as shown below in the timing report snippet.

Virtex-6, -3, 6.25 Gb/s
7-series, -3, 6.25 Gb/s
7-series, -1, 5.0 Gb/s


Slack: -0.605ns (requirement - (data path - clock path skew + uncertainty))
Source: srio_dut_inst/srio_wrapper_inst/top_inst/U0/phy_core_inst/phy_top_inst/ollm_rx_top_inst/ollm_rx_datapath_inst/PR_send_pna (FF)
Destination: srio_dut_inst/srio_wrapper_inst/top_inst/U0/phy_core_inst/phy_top_inst/ollm_tx_top_inst/ollm_tx_cs_gen_inst/parameter1_0_4 (FF)
Requirement: 3.200ns
Data Path Delay: 3.568ns (Levels of Logic = 7)
Clock Path Skew: -0.045ns (0.616 - 0.661)
Source Clock: srio_dut_inst/phy_clk rising at 0.000ns
Destination Clock: srio_dut_inst/phy_clk rising at 3.200ns
Clock Uncertainty: 0.192ns

Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.125ns
Phase Error (PE): 0.120ns


This is a known issue to be fixed in a future release of the core.

Revision History
07/25/2012 - Initial release

Linked Answer Records

Master Answer Records

AR# 50883
Date Created 07/23/2012
Last Updated 03/05/2013
Status Active
Type Known Issues
  • ISE Design Suite - 14.2
  • Vivado - 2012.2
  • Serial RapidIO