In 2012.2, only ModelSim and the Vivado Simulator are supported for encrypted IP.
To simulate IP with other simulators, you will need to create a structural model. This will be resolved as more simulators add support for IEEE P1735 Encrypted IP.
- In the GUI, Set IP as Top, run synthesis.
- After synthesis is complete, you can write out a back annotated simulation model for the IP by running the following commands from the TCL console accessible from the GUI.
- write_verilog -mode funcsim <corename>.v (for Verilog)
- write_vhdl -mode funcsim <corename>.vhd (for VHDL)
- Add the model as a simulation only source for the flow to simulate the IP.
Note: In the event that an encrypted Verilog source has an include file, the included source(s) will need to be added separately in the simulator. This is because the Xilinx encrypted HDL sources are re-encrypted to a new directory and passed onto modelsim, but if a core has an encrypted verilog include file, the incdir is not updated to point to the new location of the encrypted file.
A workaround is to set the +incdir property for Vlog as in the following example.
set_property -name modelsim.vlog_more_options -value +incdir+/proj/project_1/example_project/rxaui_v2_3_0.sim/sim_1/.srcs/rxaui_v2_3_0/rxaui_v2_3 -objects [get_filesets sim_1]