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AR# 50918

LogiCORE IP Block Memory Generator - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator tool LogiCORE IP Block Memory Generator.

The following information is listed for each version of the core:

    • General Information
    • New Features
    • Bug Fixes
    • Known Issues
    • Technical Support

General Information

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

For the most recent updates to the IP installation instructions for this core, go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator solution.

For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm

Solution

Technical Support

To obtain technical support, create a WebCase at www.xilinx.com/support, questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

LogiCORE IP ;Block Memory Generator v7.3

New Features

ISE

  • 14.3 tool support

Vivado

  • 2012.3 tool support


Supported Devices

The following device families are supported by the core for this release.

ISE

  • All 7 Series devices
  • Zynq-7000 devices
  • All Virtex-6 devices
  • All Spartan-6 devices
  • All Virtex-5 devices
  • All Spartan-3 devices
  • All Virtex-4 devices

Vivado

  • All 7 Series devices
  • Zynq-7000 devices

Resolved Issues

The following issues are resolved in Block Memory Generator v7.3:

ISE

  • N/A

Vivado

  • N/A

Known Issues

The following are known issues for v7.3 of this core at time of release:

  • Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
  • Core does not generate for large memories. Depending on the machine the ISE CORE Generator software runs on, the maximum size of the memory that can be generated will vary. For example, a Dual Pentium-4 server with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes - CR 415768 (Xilinx Answer Record 24034).

Block Memory Generator v7.2

New Features

ISE

  • ISE 14.2 design tools support

Vivado

  • 2012.2 tool support

Supported Devices

ISE

The following device families are supported by the core for this release.

  • All 7 series devices
  • Zynq-7000 devices
  • All Virtex-6 devices
  • All Spartan-6 devices
  • All Virtex-5 devices
  • All Spartan-3 devices
  • All Virtex-4 devices

Vivado

  • All 7 series devices
  • Zynq-7000 devices

Resolved Issues

The following issues are resolved in Block Memory Generator v7.2:

ISE

  • NA

Vivado

  • NA

Known Issues

ISE

The following are known issues for v7.2 of this core at time of release:

  1. Virtex-6 and Spartan-6: Block RAM Memory collision error, when the user selects TDP (write_mode= Read First)
    Work-around: The user must review the possible scenarios that causes the collision and revise their design to avoid those situations.
    • CR588505

Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with Write Mode = Read First in conjunction with asynchronous clocking.

  1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
  2. Core does not generate for large memories. Depending on the machine the ISE CORE Generator software runs on, the maximum size of the memory that can be generated will vary. For example, a Dual Pentium-4 server with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes

Vivado

  • NA

New Features

ISE

  • ISE 14.1 design tools support
  • Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, and Automotive Zynq device support.

Vivado

  • 2012.1 software support
  • Defense Grade Virtex-7Q, Kintex-7Q, Artix-7Q and Zynq-Q, Defense Grade Lower Power Kintex-7QL and Artix-7QL, and Automotive Zynq device support.

Supported Devices

The following device families are supported by the core for this release:

  • All 7 series devices
  • Zynq-7000 devices
  • All Virtex-6 devices
  • All Spartan-6 devices
  • All Virtex-5 devices
  • All Spartan-3 devices
  • All Virtex-4 devices

Vivado

  • All 7 Series devices
  • Zynq-7000 devices

Resolved Issues

The following issues are resolved in Block Memory Generator v7.1:

ISE

  • NA

Vivado

  • NA

Known Issues

ISE

The following are known issues for v7.1 of this core at time of release:

  1. Virtex-6 and Spartan-6: block RAM Memory collision error, when the user selects TDP (write_mode= Read First)
    Work-around: The user must review the possible scenarios that cause the collision and revise their design to avoid those situations.
    • CR588505

      Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with Write Mode = Read First in conjunction with asynchronous clocking.

  2. Power estimation figures in the data sheet are preliminary for Virtex-5 and Spartan-3.
  3. Core does not generate for large memories. Depending on the machine the ISE CORE Generator software runs on, the maximum size of the memory that can be generated will vary. For example, a Dual Pentium-4 server with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes

Vivado

  • NA

Block Memory Generator v6.3

New Features

  • ISE 13.4 design tools support
  • Virtex-7L, Kintex-7L, Artix-7 and Zynq-7000* device support

Resolved Issues

The following issues are resolved in Block Memory Generator v6.3:

  • Core accepts invalid write width when softecc is selected

Known Issues

The following are known issues for v6.3 of this core at the time of release:

  • Virtex-6 and Spartan-6 FPGA: Block RAM Memory collision error, when the user selects TDP (write_mode= Read First)
    Work around: The user must review the possible scenarios that causes the collision and revise their design to avoid those situations.
    NOTE: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory with Write Mode = Read First in conjunction with asynchronous clocking.
  • Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3 devices.
  • Core does not generate for large memories. Depending on the machine the ISE CORE Generator software runs on, the maximum size of the memory that can be generated will vary. For example, a Dual Pentium-4 server with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes.

LogiCORE IP Block Memory Generator v6.2

New Features

  • ISE 13.2 design tools support
  • Virtex-7L, Kintex-7L, Artix-7 and Zynq-7000* device support

Resolved Issues

  • Core errors in NGDBuild when the depth is too large (especially for Spartan-6 devices)
  • Pop-up error if block RAM utilization exceeds device capabilities
  • Default interface option should be Native BMG even if the customer does not use the AXI interface

Known Issues

  • Virtex-6 and Spartan-6: block RAM Memory collision error, when the user selects TDP (write_mode= Read First)
    Work-around: The user must review the possible scenarios that causes the collision and revise their design to avoid these situations.
    Note: For more information, see the Spartan-6 FPGA Block RAM Resources User Guide (UG383), "Conflict Avoidance" section when using TDP Memory - with Write Mode = Read First with asynchronous clocking.
  • Power estimation figures in the data sheet are preliminary for Virtex-5 and Spartan-3.
  • Core does not generate for large memories. Depending on the machine that the ISE CORE Generator software runs on, the maximum size of the memory that can be generated varies. For example, a Dual Pentium-4 server with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes.
  • Out-of-range address input can cause the core to generate Xs on the DOUT bus.
  • When the IP core is generated for Spartan-6 devices, the core does not combine two adjacent 9K block RAMs into one 18K block RAM.

LogiCORE IP Block Memory Generator v6.1

New Features

  • ISE 13.1 design tools support
  • Virtex-7 and Kintex-7 device support
  • AXI4/AXI4-Lite interface support for Virtex-6 and Spartan-6 devices
  • Virtex-7, Kintex-7 device support

Resolved Issues

The following issues are resolved in Block Memory Generator v6.1:

  • "Fill remaining memory locations" - option disabled in GUI
  • Version fixed : 6.1

(Xilinx Answer 37944) Core does not allow the customer to use the "remaining memory locations" option.

Solution: "Fill remaining memory locations" - option enabled in GUI

Known Issues

The following are known issues for v6.1 of this core at time of release:

  • (Xilinx Answer 40059) Core errors in NGDBuild when the depth is too large (especially for Spartan-6 devices)
    The user has to generate two or more netlists based on the memory configurations and pass the appropriate address lines to achieve the required functionality
  • (Xilinx Answer 34859) Virtex-6 block RAM Memory collision error, when the user selects TDP (write_mode= Read First) User will have to consider collision Issue
  • (Xilinx Answer 34533 ) Spartan-6 block RAM Memory collision error, when the user selects TDP (write_mode= Read First) User will have to consider collision Issue
    Note: Refer to UG383, 'Conflict Avoidance' section while using TDP Memory, with Write Mode = Read First in conjunction with asynchronous clocking
  • (Xilinx Answer 24034) Core does not generate for large memories. Depending on the machine the ISE CORE Generator software runs on, the maximum size of the memory that can be generated will vary. For example, a Dual Pentium-4 server with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
  • (Xilinx Answer 23744) Out-of-range address input can cause the core to generate Xs on the DOUT bus
  • (Xilinx Answer 40004) When the IP core is generated for Spartan-6 devices, the core should combine two adjacent 9k block RAMs into one 18K block RAM.

LogiCORE IP Block Memory Generator v4.3

New Features

  • None

Resolved Issues

  • None

Known Issues

  • Virtex-6 FPGA Block RAM Memory collision error
    When the user selects TDP (write_mode= Read First)
    Impact: User will have to consider the collision issue.

  • Spartan-6 FPGA Block RAM Memory collision error
    When the user selects TDP (write_mode= Read First)
    Impact: User will have to consider collision issue

    NOTE: Refer to UG383, 'Conflict Avoidance' section while using TDP Memory, with Write Mode = Read First in conjunction with asynchronous clocking.
  • Power estimation figures in the datasheet are preliminary
  • Core does not generate for large memories. Depending on the machine the ISE CORE Generator software runs on, the maximum size of the memory that can be generated will vary. For example, a Dual Pentium-4 server with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
  • CR 415768
  • (Xilinx Answer 24034) LogiCORE Block Memory Generator - Generating Block Memory Generator takes a long time
  • Out-of-range address input can cause the core to generate Xs on the DOUT bus
  • (Xilinx Answer 23744) LogiCORE Block Memory Generator - Invalid address on ADDR can cause the core to generate Xs on the DOUT bus during simulation
  • When the IP core is generated for Spartan-6 devices, the core should combine two adjacent 9k block RAM into one 18K block RAM.
  • CR 526429

LogiCORE IP Block Memory Generator v4.2

New Features

  • ISE 12.2 design tools support
  • Soft-ECC support for Virtex-6 and Spartan-6 devices

Resolved Issues

  1. Virtex-6 block RAM Memory collision error
    • When the user selects SDP - in Virtex-6 devices
      Solution: For SDP configuration, the write_mode is set as Read_First when Common Clock is enabled otherwise the write_mode is set as Write_First
    • CR 564035
    • CR 557149

Known Issues

The following are known issues for v4.2 of this core at time of release:

Additional Memory Collision Restrictions: Address Space Overlap

  • Virtex-6 block RAM Memory collision error
    When the user selects TDP (write_mode= Read First)
    Impact: User will have to consider collision Issue

  • Spartan-6 block RAM Memory collision error
    When the user selects TDP (write_mode= Read First)
    Impact: User will have to consider collision Issue
    Note: Refer to UG383, 'Conflict Avoidance' section while using TDP Memory, with Write Mode = Read First in conjunction with asynchronous clocking.

    When the user selects SDP ? Fixed Primitives ? 256 x 36:
    • Internally, the core will use 512 x 36 primitives.
    • The memory utilization may double based on the user depth x width selection.
    When the user selects SDP ? Minimum Area or Low Power algorithm:
    • Internally, the core will use 512 x 36 primitives instead of 256 x 36 primitives.
    • The memory utilization may double based on the user depth x width selection.

LogiCORE IP Block Memory Generator style="display: inline-block"> v4.1

New Features

  • ISE 12.1 design tools support
  • Virtex-6Q and Spartan-6Q device support

Resolved Issues

  • Virtex-6 FPGA Block RAM Memory collision error
    Version fixed : 4.1

    When the user selects SDP - Fixed Primitives - 512x72 or 512x36
    Solution: Internally core will use two 1024x36 or two 1024x18 primitives respectively
    Impact: Memory utilization will double.

    When the user selects SDP - Minimum Area or Low Power algorithm
    Solution: Internally core will not use 512x72 and 512x36 primitives
    Impact: Memory utilization may double based on user depth x width selection
    (Xilinx Answer 34259)

    Note: Refer to DS512, 'Collision Behavior' and 'Work-around' sections for Primitive usage restrictions, above work-arounds can be disabled by enabling 'Common Clock' option in Page 5".

  • Spartan-6 FPGA Block RAM Memory collision error & Spartan-6 FPGA Port Width issue
    Version fixed : 4.1

    When the user selects SDP Fixed Primitives 256 x 36
    Solution: Internally, the core will use 512 x 36 primitives, respectively
    Impact: The memory utilization could double based on user depth x width selection.

    When the user selects SDP Minimum Area or Low Power algorithm
    Solution: Internally, the core will use 512 x 36 primitives instead of 256 x 36 primitives
    Impact: The memory utilization could double based on the user depth x width selection
    (Xilinx Answer 34699)

    Note: Refer to DS512, 'Collision Behavior' and 'Work-around' sections for Primitive usage restrictions, above work-arounds can be disabled by enabling 'Common Clock' option in Page 5".

Known Issues

The following are known issues for v4.1 of this core at time of release:

  • Virtex-6 FPGA block RAM Memory collision error

    When the user select ECC (option supported only with RAMB36E1 512x72 primitive)
    Impact: User will have to consider collision issue.

    When the user selects TDP (write_mode= Read First)
    Impact: User will have to consider collision Issue

    For generated cores with Muxing Stages enabled, It is recommended to recreate the core using CORE Generator Flow and re-select the muxing stages 7.

    Note: Refer to UG363, 'Conflict Avoidance' section while using ECC Mode or TDP Memory, with Write Mode = Read First and with asynchronous clocking".

  • Spartan-6 FPGA block RAM Memory collision error
    When the user selects TDP (write_mode= Read First)
    Impact: User will have to consider collision issue.

    Note: Refer to UG383, 'Conflict Avoidance' section while using TDP Memory, with Write Mode = Read First and with asynchronous clocking".

  • Power estimation figures in the data sheet are preliminary.
  • Core does not generate for large memories. Depending on the machine the ISE CORE Generator software runs on, the maximum size of the memory that can be generated will vary. For example, a Dual Pentium-4 server with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
  • Out-of-range address input can cause the core to generate X's on the DOUT bus
  • CORE Generator GUI Console displays error "For the configured RAM size, the number of block RAMs used exceeds the maximum number of 18KB block RAMs in the chosen architecture.
  • When the IP core is generated for Spartan-6 devices, the core should combine two adjacent 9k block RAMs into one 18K block RAM.
    • CR 526429

LogiCORE IP Block Memory Generator style="display: inline-block"> v3.3

New Features

  • ISE 11.3 design tools support
  • Virtex-6 Lower Power and Virtex-6 HXT device support
  • Spartan-3A/-3A DSP Automotive device support
  • Power estimation reporting in CORE Generator GUI

Resolved Issues

  • Byte write enables incorrectly disabled in CORE Generator IP customization GUI when Spartan-3A device is selected
    • Version fixed: 3.3
    • CR 525957
    • In version 3.2 the Byte Write Enable was disabled for Spartan-3A devices.
    This has been re-enabled so that the user can now choose to set or unset Byte Write Enable.

  • Async reset support not enabled in CORE Generator IP customization GUI when Spartan-6 device is selected Async reset support has been enabled in CORE Generator IP customization GUI for Spartan-6 devices. However, the Xilinx synthesis tool generates a warning "Xst:2940 - This design infers one or more latches or registers with both an active asynchronous set and reset."

  • Special reset behavior not seen on core output in Virtex-6 devices
    • Version fixed : 3.3
    • CR 520553
    • There is a limitation in supporting special reset behavior with the priority set to SR based on limitations in the associated Virtex-6 FPGA primitive, hence the IP has been updated to support special reset behavior when the reset priority is set to CE only.

  • In Block Memory Generator data sheet, the resource utilization for Spartan-3 FPGA is incorrect

Known Issues

  • Power estimation figures in the data sheet are preliminary.
  • (Xilinx Answer 31377) CORE Generator GUI Console displays error "For the configured RAM size, the number of block RAMs used exceeds the maximum number of 18KB block RAMs in the chosen architecture"
  • (Xilinx Answer 24034) Core does not generate for large memories
    • The maximum size of the memory that can be generated varies depending on the machine the CORE Generator is run on. For example, a Dual Pentium-4 server running at 3.6 GHz with two Gig RAM can generate a memory core that is 1.8 MBits or 230 KBytes.
    • CR 415768

  • (Xilinx Answer 23744) Out-of-range address input can cause the core to generate Xs on the DOUT bus Why do I see setup violations when I simulate my Virtex-6 FPGA SDP memory?

LogiCORE IP Distributed Memory Generator v3.2

New Features

  • Support for Virtex-6 and Spartan-6 devices

Resolved Issues

  • Number of Pipeline stages within Mux unavailable for Spartan-6
    Version fixed : 3.2
    CR 510812
    In previous versions of the core, the multiplexer size reported on the CORE Generator GUI was 1 even though the multiplexer size was greater than 1, as a result of which the user was not able to select the number of Pipeline Stages within a Mux.

Known Issues

  • Virtex-6 and Spartan-6 solutions are pending hardware validation
  • Software Support for the Virtex-6 Lower Power parts was added in this release, but Block Memory Generator is not yet supported and cannot be generated from CORE Generator. In order to work around this issue, you can set your project to target an equivalent Virtex-6 LXT device which will allow you to generate a place holder IP that can be regenerated when support for the Virtex-6 Lower Power parts is added in 11.3.
  • Power estimation figures in the data sheet are preliminary.
  • (Xilinx Answer 31377) CORE Generator GUI Console displays error "For the configured RAM size, the number of block RAMs used exceeds the maximum number of 18KB block RAMs in the chosen architecture"
  • (Xilinx Answer 24034) Core does not generate for large memories
    • The maximum size of the memory that can be generated varies depending on the machine the CORE Generator is run on. For example, a Dual Pentium-4 server running at 3.6GHz with two Gig RAM can generate a memory core that is 1.8 MBits or 230 K Bytes.
    • CR 415768
  • (Xilinx Answer 23744) Out-of-range address input can cause the core to generate Xs on the DOUT bus) Asynchronous reset not supported in Spartan-6
    • CR 521107

LogiCORE IP Distributed Memory Generator v3.1

New Features

  • Display of block RAM utilization in terms of 9K, 18K and 36K primitives
  • Support for Low Power algorithm (Virtex-5, Virtex-4, and Spartan-3/-3E/-3A/-3AN/-3ADSP)
  • Disabled option to keep a port Always Enabled while using the Low Power algorithm

Resolved Issues

  • - Estimated BlockRAM Usage is incorrect
    - Version fixed : 3.1
    - CR 491178, 481514
    - In previous versions of the core, the block RAM utilization was always reported in terms of 18K primitives, as a result of which the actual block RAM utilization was different from the number reported when 36K primitives were used. The GUI will now report block RAM utilization separately in terms of 9K, 18K and 36K blocks.
  • (Xilinx Answer 32290) READ_FIRST mode does not work as expected in Virtex-5 Single Primitive ECC configurations
    • Version fixed : 3.1
    • CR 498772
  • (Xilinx Answer 32037) Discrepancy in latency reported in GUI for ECC configurations
    • Version fixed : 3.1
    • CR 501642, 493653
  • Migration from Behaviorial model to structural model does not flow smoothly
    • Version fixed : 3.1
    • CR 475649

Known Issues

  • Power estimation figures in the data sheet are preliminary.
  • (Xilinx Answer 31377) CoreGen GUI Console displays error "For the configured RAM size, the number of block RAMs used exceeds the maximum number of 18KB block RAMs in the chosen architecture"
  • (Xilinx Answer 24034) Core does not generate for large memories
    • The maximum size of the memory that can be generated varies depending on the machine the CORE Generator is run on. For example, a Dual Pentium-4 server running at 3.6GHz with two Gig RAM can generate a memory core that is 1.8 MBits or 230 K Bytes.
    • CR 415768
  • (Xilinx Answer 23744) Out-of-range address input can cause the core to generate Xs on the DOUTbus

LogiCORE IP Distributed Memory Generator v2.8

New Features

  • Virtex-5 TXT support
  • New Low Power implementation option to reduce power consumption by the core
  • Customization GUI now reports the exact size of the MUX used for pipelining for all algorithms

Resolved Issues

  • Power utilization the same for single port configurations and dual port configurations of the core. (In previous versions of the core, Port B was always enabled by default. Hence, single port configurations resulted in the same power utilization as dual port configurations. This has now been changed and Port B is disabled in single port configurations.)
    • CR 430719
  • The customization GUI for the v2.7 core does not display the ECC option for Virtex-5 single port RAM configurations.
    • CR 468611
  • (Xilinx Answer 30401) Block Memory Generator GUI crashes when certain ranges of Write Depth and Write Width values are
    selected
    • CR 433002
  • Block Memory Generator resource utilization for single port configurations is double that of the legacy single port Block Memory core for Spartan-3 and Virtex-II derivative families. (The extra wide 256x72 primitive available for single port configurations was not being implemented for Spartan-3 and Virtex-II derivative families.)
    • CR 469821

Known Issues

  • (Xilinx Answer 32290) READ_FIRST mode does not work in Virtex-5 Single Port ECC configurations
  • (Xilinx Answer 32037) CORE Generator GUI displays the incorrect latency for an ECC enabled core
  • (Xilinx Answer 24034) Core does not generate for large memories
    The maximum size of the memory that can be generated varies depending on the machine the CORE Generator is run on. For example, a Dual Pentium-4 server running at 3.6GHz with two Gig RAM can generate a memory core that is 1.8 MBits or 230 K Bytes.
    • CR 415768
  • (Xilinx Answer 23744) Out-of-range address input can cause the core to generate Xs on the DOUT bus

LogiCORE IP Block Memory Generator v2.7

New Features

  • ISE 10.1 design tools support.
  • Improved behavioral simulation time over the v2.6 core.

Resolved Issues

  • Generating Block Memory Generator takes a long time.
    • CR 444402
  • (Xilinx Answer 24313) When using the core for Virtex-4 and Virtex-5 with Byte-write Enable and Write-First Operating Mode, the following warning might be displayed during simulation:
    "# ** Warning: Functional warning at simulation time ( 1572 ns)
    : RAMB16( :top:bm_tb:test1_dut:bmg0:bmg0:bu2_u0_blk_mem_generator_
    valid_cstr_ramloop_0_ram_r_v4_ram_true_dp_single_prim_tdp:)
    port A is in WRITE_FIRST mode requiring all bits of WEA to be all
    '1's or all '0's to guarantee valid outputs.
    # Time: 1572 ns Iteration: 3 Instance:
    /top/bm_tb/test1_dut/bmg0/bmg0/bu2_u0_blk_mem_generator_valid_cstr_
    ramloop_0_ram_r_v4_ram_true_dp_single_prim_tdp"
  • Block Memory Generator GUI incorrectly allows you to select any of the three write modes in the Simple Dual-Port RAM: Simple Dual-Port RAM must allow the Read First mode only.
    • CR 436053
  • Block Memory Generator GUI does not have validation checks for Enable_B and Use_Ramb16bwer_Reset_Behavior, causing failure in generation of ASY symbol and Core netlist respectively.
    • CR 439672, CR 433594

Known Issues

  • (Xilinx Answer 32037) CORE Generator GUI displays the incorrect latency for an ECC enabled core
  • (Xilinx Answer 24034) Core does not generate for large memories
    The maximum size of the memory that can be generated varies depending on the machine the CORE Generator is run on. For example, a Dual Pentium-4 server running at 3.6 GHz with two Gigabytes of RAM can generate a memory core that is 1.8 MBits or 230 kilobytes.
    • CR 415768
  • (Xilinx Answer 23744) Out-of-range address input can cause the core to generate Xs on the DOUT bus
  • (Xilinx Answer 30401) Block Memory Generator GUI crashes when certain ranges of Write Depth and Write Width values are
    selected
    • CR 433002

LogiCORE IP Block Memory Generator v2.6

New Features

Support for pipeline stages within the mux where applicable

Resolved Issues

  • (Xilinx Answer 24804) Block Memory Generator GUI fails with an internal error if no value is entered for Write Depth
    • CR 432931

Known Issues

  • (Xilinx Answer 24034) Core does not generate for large memories. Depending on the machine the CORE Generator runs on, the maximum size of the memory that can be generated will vary. For example, a Dual Pentium-4 server running at 3.6GHz with 2 Gig RAM can generate a memory core of a size 1.8 MBits or 230 K Bytes.
    • CR 415768
  • (Xilinx Answer 23744) Out-of-range address input can cause the core to generate X's on the DOUT bus.
  • (Xilinx Answer 24313) When using the core for Virtex-4 and Virtex-5 with Byte-write Enable and Write-First Operating Mode, the following warning might be displayed during simulation:
    # ** Warning: Functional warning at simulation time ( 1572 ns)
    : RAMB16( :top:bm_tb:test1_dut:bmg0:bmg0:bu2_u0_blk_mem_generator_
    valid_cstr_ramloop_0_ram_r_v4_ram_true_dp_single_prim_tdp:)
    port A is in WRITE_FIRST mode requiring all bits of WEA to be all
    '1's or all '0's to guarantee valid outputs.
    # Time: 1572 ns Iteration: 3 Instance:
    /top/bm_tb/test1_dut/bmg0/bmg0/bu2_u0_blk_mem_generator_valid_cstr_
    ramloop_0_ram_r_v4_ram_true_dp_single_prim_tdp

LogiCORE IP Block Memory Generator v2.5

New Features

  • Byte Write Enable support for Spartan-3A/3A DSP devices
  • Separate output register controls for Port A and Port B
  • New Core Generator feature: upgrades Block Memeory Generator v2.4 to v2.5 from the Core Generator GUI.
    See the "Upgrading a Core" section of the Core Generator User Guide (Software Manuals).

Resolved Issues

CR 435009: Deep Single-Port RAM or ROM configurations of the core are implemented by cascading the 32kx1 primitive (Virtex-4) or the 64kx1 primitive (Virtex-5). DRC checks fail in these implementations because the cascade in/out pins for port B are not connected

Known Issues
(Xilinx Answer 29168) v2.5 XCO parameters have changed
(Xilinx Answer 23688) Block Memory Generator GUI will not open on Linux and Solaris when project directory is in "$XILINX"
(Xilinx Answer 23744) Invalid address input can cause the core to generate Xs on the DOUT bus
(Xilinx Answer 24034) Block Memory Generator Core takes a long time to generate
(Xilinx Answer 24313) The core might issue unexpected outputs and simulation warning: "# ** Warning: Functional warning at simulation time ..."
(Xilinx Answer 24804) ERROR:sim:166 - An internal error has occurred. Closing core customization GUI.

LogiCORE IP Block Memory Generator style="display: inline-block"> v2.4.1

New Features

  • Support for ECC (built-in Hamming error correction) in Virtex-5

Resolved Issue style="display: inline-block">s

  • CR 429967: Block Memory Generator wastes resources (is non-optimal for certain configurations)
  • CR 415531: Block Memory Generator GUI displays unselectable options

Known Issues

  • (Xilinx Answer 23688) Block Memory Generator GUI will not open on Linux and Solaris when project directory is in "$XILINX"
  • (Xilinx Answer 23744) Invalid address input can cause the core to generate Xs on the DOUT bus
  • (Xilinx Answer 24034) Block Memory Generator Core takes a long time to generate
  • (Xilinx Answer 24313) The core might issue unexpected outputs and simulation warning: "# ** Warning: Functional warning at simulation time ..."
  • (Xilinx Answer 24804) ERROR:sim:166 - An internal error has occurred. Closing core customization GUI.
  • (Xilinx Answer 24860) When using Single Port ROM/RAM, BitGen gives "ERROR:PhysDesignRules:1530 - Dangling pins on block:../blk_mem_generator/SP.CASCADED_PRIM36.."

LogiCORE IP Block Memory Generator style="display: inline-block"> v2.4

New Features style="display: inline-block">

  • Support for ECC (built-in Hamming error correction) in Virtex-5

Resolved Issues

  • CR 429967: Block Memory Generator wastes resources (is non-optimal for certain configurations)
  • CR 415531: Block Memory Generator GUI displays unselectable options

Known Issues

  • (Xilinx Answer 23688) Block Memory Generator GUI will not open on Linux and Solaris when project directory is in "$XILINX"
  • (Xilinx Answer 23744) Invalid address input can cause the core to generate Xs on the DOUT bus
  • (Xilinx Answer 24034) Block Memory Generator Core takes a long time to generate
  • (Xilinx Answer 24313) The core might issue unexpected outputs and simulation warning: "# ** Warning: Functional warning at simulation time ..."
  • (Xilinx Answer 24804) ERROR:sim:166 - An internal error has occurred. Closing core customization GUI.
  • (Xilinx Answer 24860) When using Single Port ROM/RAM, BitGen gives "ERROR:PhysDesignRules:1530 - Dangling pins on block:../blk_mem_generator/SP.CASCADED_PRIM36.."

LogiCORE IP Block Memory Generator v2.3

New Features

  • None

Resolved Issues

  • (Xilinx Answer 24104) When using Byte Write Enable feature, the data read-out from the memory might not match what is expected.
  • (Xilinx Answer 24061) Unexpected data is seen on the output as the memory is generated with the incorrect write mode.
  • (Xilinx Answer 24069) Memory is not initialized correctly using the COE or "Filling Memory Locations" option.
  • (Xilinx Answer 24033) Block Memory Resource Estimate (on last page of GUI) reports "undefined".
  • (Xilinx Answer 24057) Spartan-3A is a supported device, although the table on page one of the data sheet "Supported Device Family" does not mention that this device is supported.

Known Issues

  • (Xilinx Answer 23688) Block Memory Generator GUI will not open on Linux and Solaris when project directory is in "$XILINX".
  • (Xilinx Answer 23744) Invalid address input can cause the core to generate Xs on the DOUT bus.
  • (Xilinx Answer 24034) Block Memory Generator Core takes a long time to generate.
  • (Xilinx Answer 24313) The core might issue unexpected outputs and simulation warning: "# ** Warning: Functional warning at simulation time ..."

LogiCORE IP Block Memory Generator style="display: inline-block"> v2.2

New Features

  • Added support for Spartan-3A, Spartan-3 XA, Spartan-3E XA, and Virtex-4 XA
  • Minimum depth has been reduced from eight to two
  • Added support for Simple Dual Port block RAM primitives in Virtex-5 FPGa

Resolved Issues

  • CR 232997: Virtex-5 timing simulation failed with SDF file error: " # ** Error: (vsim-SDF-3261) ../../implement/results/routed.sdf(1200): Failed to find matching module path."
  • CR: 232994: The Verilog NetGen-generated model failed consistently for Virtex-5, producing incorrect outputs from the RAMB36 primitive on the DOUT during simulation.
    This is a UniSim model issue and is fixed in 8.2i Service Pack1.
  • (Xilinx Answer 23686) Virtex-4, in structural (UniSim) simulation DOUTA changes on the wrong clock.
  • (Xilinx Answer 22699) Behavioral models did not flag collision for asymmetric read-write ports. Block Memory Generator v2.2 now flags collision for asymmetric read-write ports.
  • (Xilinx Answer 23682) Data sheet lacked the information on differences between older memory cores and the new Block Memory Generator when using one port as Read-Only.

Known Issues

  • CR 232997: Virtex-5 timing simulation failed with SDF file error: " # ** Error: (vsim-SDF-3261) ../../implement/results/routed.sdf(1200): Failed to find matching module path."
    This is a NetGen SDF file generator issue and is fixed in ISE 8.2i Service Pack 1.
  • CR: 232994: The Verilog NetGen-generated model failed consistently for Virtex-5, producing incorrect outputs from the RAMB36 primitive on the DOUT during simulation.
    This is a UniSim model issue and is fixed in 8.2i Service Pack1.
  • (Xilinx Answer 24104) When using Byte Write Enable feature, the data read-out from the memory might not match what is expected.
  • (Xilinx Answer 24061) Unexpected data is seen on the output as the memory is generated with the incorrect write mode.
  • (Xilinx Answer 24069) Memory is not initialized correctly using COE or "Filling Memory Locations" option.
  • (Xilinx Answer 24057) Spartan-3A is a supported device, although the table on page one of the data sheet "Supported Device Family" does not mention that this device is
  • supported.
  • (Xilinx Answer 24033) Block Memory Resource Estimate (on last page of GUI) reports "undefined" .
  • (Xilinx Answer 23688) Block Memory Generator GUI will not open on Linux and Solaris when project directory is in "$XILINX".
  • (Xilinx Answer 23744) Invalid address input can cause the core to generate X's on the DOUT bus.
  • (Xilinx Answer 24034) Block Memory Generator Core takes a long time to generate.

LogiCORE IP Block Memory Generator style="display: inline-block"> v2.1

New Features

  • Added support for Spartan-3A, Spartan-3 XA, Spartan-3E XA, and Virtex-4 XA
  • Minimum depth has been reduced from eight to two
  • Added support for Simple Dual Port block RAM primitives in Virtex-5

Resolved Issues

  • (Xilinx Answer 23686) Virtex-4, in structural (UniSim) simulation DOUTA changes on the wrong clock.
  • (Xilinx Answer 22699) Behavioral models did not flag collision for asymmetric read-write ports. Block Memory Generator v2.2 now flags collision for asymmetric read-write ports.
  • (Xilinx Answer 23682) Data sheet lacked the information on differences between older memory cores and the new Block Memory Generator when using one port as Read-Only.

Known Issues

  • (Xilinx Answer 24104) When using Byte Write Enable feature, the data read-out from the memory might not match what is expected.
  • (Xilinx Answer 24061) Unexpected data is seen on the output as the memory is generated with the incorrect write mode.
  • (Xilinx Answer 24069) Memory is not initialized correctly using COE or "Filling Memory Locations" option.
  • (Xilinx Answer 24057) Spartan-3A is a supported device, although the table on page one of the data sheet "Supported Device Family" does not mention that this device is supported.
  • (Xilinx Answer 24033) Block Memory Resource Estimate (on last page of GUI) reports "undefined" .
  • (Xilinx Answer 23688) Block Memory Generator GUI will not open on Linux and Solaris when project directory is in "$XILINX".
  • (Xilinx Answer 23744) Invalid address input can cause the core to generate X's on the DOUT bus.
  • (Xilinx Answer 24034) Block Memory Generator Core takes a long time to generate.
AR# 50918
Date Created 07/20/2012
Last Updated 11/06/2013
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • ISE Design Suite
IP
  • Block Memory Generator