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AR# 50925: 14.2 EDK, Zynq-7000 - ERROR:EDK - IPNAME: processing_system7 - PARAMETER C_S_AXI_GP0_ID_WIDTH has value 7 which does not fall in the range (1 : 6)
14.2 EDK, Zynq-7000 - ERROR:EDK - IPNAME: processing_system7 - PARAMETER C_S_AXI_GP0_ID_WIDTH has value 7 which does not fall in the range (1 : 6)
When using a Zynq-7000 design, the following error occurs:
ERROR:EDK - IPNAME: processing_system7, INSTANCE: processing_system7_0 - PARAMETER C_S_AXI_GP0_ID_WIDTH has value 7 which does not fall in the range (1 : 6 ), specified in MPD
How do I resolve this issue?
This error message is correct -- the Zynq-7000 AXI ACP, HP, and HP interfaces each have maximum ID width that they can be connected to. This error message indicates that the maximum has been exceeded and must be reduced to the range specified.
AXI ID width increases by the number of masters attached to an AXI Interconnect and the ID of each master itself. It is also important to note that currently the Xilinx AXI Interconnect increases the ID width globally from all masters, irrespective of actual connectivity chosen in the crossbar.
Also note that the Zynq PS GP master ports have an ID width of 12 bits each, more than any PS AXI slave interfaces total ID width. The master ID width can be reduced to 6 bits through ID remapping on the processing_system7 wrapper, but still only leaves 1 ID bit for one more single-threaded master in the Zynq PL. Thus, the main method to reduce ID width connected to PS AXI slave ports is to segment the PS GP master port connections. Any AXI Interconnects which drive a PS AXI slave interface must not be driven by a PS AXI master, or another Interconnect connected to an AXI master.
In cases with many AXI masters, segmentation may also be necessary to reduce ID width driving a PS slave interface.
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EDK - 14.1
EDK - 14.2
Processing System 7
Boards & Kits
Zynq-7000 SoC ZC702 Evaluation Kit