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AR# 50929 AutoESL - Zynq EPP Design Example with AXI-DMA Core for Data Transfer

Description

This answer record contains the Zynq EPPdesign example with AXI-DMA core for data transfer.

Solution

The documentationand design file(AutESL_Zynq_Training_Labs.pdf, and autoesl_zynq_training_labs.zip) thatare linked at the end of thisanswer recordprovide the following exercises:

  • Create a basic Zynq EPP system
  • Instantiate an AutoESL generated block in a Zynq EPP system
  • Debug the communication between AutoESL generated IP and ARM
  • Connect two AutoESL IPs using AXI4-streaming
  • Use the AXI-DMA core for data transfers to external memory from AutoESL IP

Attachments

Associated Attachments

Name File Size File Type
AutESL_Zynq_Training_Labs.pdf 4 MB PDF
autoesl_zynq_training_labs.zip 45 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A

Actions

AR# 50929
Date Created 07/20/2012
Last Updated 03/02/2013
Status Active
Type Solution Center
Tools
  • AutoESL
  • AutoESL - 2012.1
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