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AR# 50929

AutoESL - Zynq AP SoC Design Example with AXI-DMA Core for Data Transfer


This answer record contains the Zynq All Programmable SoC design example with AXI-DMA core for data transfer.


The documentation and design file (AutESL_Zynq_Training_Labs.pdf, and autoesl_zynq_training_labs.zip) that are linked at the end of this answer record provide the following exercises:

  • Create a basic Zynq AP SoC system
  • Instantiate an AutoESL generated block in a Zynq AP SoC system
  • Debug the communication between AutoESL generated IP and ARM
  • Connect two AutoESL IPs using AXI4-streaming
  • Use the AXI-DMA core for data transfers to external memory from AutoESL IP


Associated Attachments

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 50929
Date Created 07/20/2012
Last Updated 12/16/2013
Status Active
Type Solution Center
  • AutoESL
  • AutoESL - 2012.1