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AR# 50941

SPI-4.2 v12. core (2012.2 release) - Using the High Range I/O When Targeting Virtex-7 and Kintex-7 Devices

Description

The example design provided with the SPI-4.2 core in v12.2 currently targets the High Performance (HP) I/O for the Sink and Source core data interfaces. It is possible to use the High Range (HR) I/O when targeting Virtex-7 and Kintex-7 devices for lower speeds. Please consult the Virtex-7 and Kintex-7 FPGAs DC and Switching Characteristics data sheets (DS182 and DS183) for the specific speeds that can be supported in the HR I/O.

Solution

To use the High Range I/O for Virtex-7 and Kintex-7 SPI-4.2 cores:

1. Update any applicable IOSTANDARD generics on I/O buffer instantiations in the example design from "LVDS" to "LVDS_25."
For the example design, these are located in <core_name>_l4_src_clk.v[hd], <core_name>_pl4_snk_clk.v[hd], and <core_name>_top.v[hd].

2. Add the following to the XDC file:
For the Source Core:
set_property IOSTANDARD LVDS_25 [get_cells <core_instant_name>/U0/pl4_src_top/*pl4_src_top/io0/src_ddr*/*ddr*_buf]
set_property IOSTANDARD LVDS_25 [get_cells <core_instant_name>/U0/pl4_src_top/*pl4_src_top/io0/src_ctl*/*ddr*_buf]
set_property IOSTANDARD LVDS_25 [get_cells <core_instant_name>/U0/pl4_src_top/*pl4_src_top/io0/TDClk_buf_v7.src_buf]
For the Dynamic Sink Core:
set_property IOSTANDARD LVDS_25 [get_cells <core_instant_name>/U0/pl4_snk_top/*pl4_snk_top/io0/*dpa/dpa_top0/*DATAPAIR*/*BUFIN*.INBUF*]
set_property IOSTANDARD LVDS_25 [get_cells <core_instant_name>/U0/pl4_snk_top/*pl4_snk_top/io0/*dpa/dpa_top0/*CTLPAIR*/*BUFIN*.INBUF*]
For the Static Sink Core:
set_property IOSTANDARD LVDS_25 [get_cells <core_instant_name>/U0/pl4_snk_top/*pl4_snk_top/io0/StaticAlign.buffer_data/*BUFIN*]

3. Update any pin LOC constraints or other placement constraints as necessary to target High Range I/O banks.
AR# 50941
Date Created 07/31/2012
Last Updated 11/28/2012
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7
IP
  • SPI-4 Phase 2 Interface Solutions