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AR# 51016 Known Issues and Work-arounds with 7 Series GTZ Transceiver Wizard in Vivado 2012.2

Description


This Answer Record covers Known Issues with v2.2 of the 7 Series FPGAs Transceivers Wizard targeting GTZ Transceivers in Vivado 2012.2 Design Suite.

1. The beachfront_placeNroute.tcl file does not work with Vivado Synthesis. A new beachfront_placeNroute.tcl file is required.

2. There is a minimum pulse width violation seen when running report_timing_summary

Solution


In order to successfully use the 7 Series Transceiver Wizard output in Vivado 2012.2, you must:
  1. Install Vivado 2012.2 Update release (2012.2.1) that is available at http://www.xilinx.com/support/download/index.htm
  2. Replace the existing beachfront_placeNroute.tcl in the output ./implement directory with the one attached to this answer record.
  3. Edit the ./example_design/gtwizard_v2_2_0_exdes.xdc XDC constraints (ensure the appropriate period for your example design is used):


For example (assuming a period of 6.206), replace:

create_clock -name rxusrclk1 -period 6.206 rxusrclk1
create_clock -name txusrclk0 -period 6.206 txusrclk0

With:
create_clock -name TXOUTCLK0 -period 6.206 [get_pins -hierarchical *gtze2_octal_north/TXOUTCLK0]
create_generated_clock -name TXUSRCLK0 -divide_by 1 -source [get_pins -hierarchical *gtze2_octal_north/TXOUTCLK0] [get_pins -hierarchical -filter {name=~*gtze2_inf_north*clkbuflbtx0*CLKOUT}]
create_clock -name RXOUTCLK0 -period 6.206 [get_pins -hierarchical *gtze2_octal_north/RXOUTCLK0];
create_clock -name DRPCLK_IN -period 20 [get_ports DRPCLK_IN]
Note: You will still see minimum pulse width violations on TXUSRCLK0 and mmcm_clk_out_rx1. These will be fixed in Vivado 2012.3 and can be safely ignored in Vivado 2012.2 Design Suite.






beachfront_placeNroute.tcl

Actions

AR# 51016
Date Created 09/11/2012
Last Updated 09/11/2012
Status Active
Type
Devices
  • Virtex-7 HT
Tools
  • Vivado - 2012.2
IP
  • 7 Series FPGAs Transceivers Wizard
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