UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 51017

Design Advisory for the Artix-7 GTP Transceiver Power-Up/Power-Down

Description

This answer record discusses the Artix-7GTP Transceiver power-up/power-down sequencing recommendations andtheir implications.

Solution

1. Recommended Power-up/Power-down Sequences

The recommended GTP transceiver power-on sequence is VCCINT, VMGTAVCC, VMGTAVTT or VMGTAVCC, VCCINT, VMGTAVTT to achieve minimum current draw. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw.

If the recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-up and power-down:

If VMGTAVTT is powered before VMGTAVCC, and VMGTAVTT - VMGTAVCC > 150 mV and VMGTAVCC < 0.7V, the VMGTAVTT current draw can increase by 460 mA per transceiver when VMGTAVCC is ramping up. The duration of the current draw may be up to 0.3* TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down.

If VMGTAVTT is powered before VCCINT, and VMGTAVTT - VCCINT > 150 mV and VCCINT < 0.7V, the VMGTAVTT current draw can increase by 50 mA per transceiver when VCCINT is ramping up. The duration of the current draw may be up to 0.3* TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down.

2. Frequently Asked Questions

1.What should these additional currents be added to when not following the recommended sequences?
For GTP Initial ES Silicon, this assumes thatXPE 14.2 version or newer is used.
If the recommended sequencesare used, there are no additional currents to be added.
If the recommended sequences are not used, then the additional currentsmentioned are added on top of the XPEnumbers.

2. Simultaneous power-up: Is it okay to simultaneously power-up VMGTAVCCand VMGTAVTT, OR VCCINTand VMGTAVTT, OR all three? Does the additional current draw still apply?
During power-up, if VMGTAVCC < 0.7V (Time "T1" in the picture) and VMGTAVTT - VMGTAVCC <= 150 mV, then there is no additional current draw. During power-up, if VMGTAVCC >= 0.7V (Time "T1" in the picture), then there is no additional current irrespective of VMGTAVTT value.

During power-up, if VMGTAVCC < 0.7V (Time "T1" in the picture) and VMGTAVTT VCCINT <= 150 mV, then there is no additional current draw. During power-up, if VCCINT >= 0.7V (Time "T1" in the picture), then there is no additional current irrespective of VMGTAVTT value.
If these conditions cannot be met, then the additional current needs to be accounted for.

3. Are these additional currents on VMGTAVTT cumulative when both sequences of VMGTAVTT vs VMGTAVCC and VMGTAVTT vs VCCINT are not followed?
The power supply current increase is cumulative. So, if both conditions occur simultaneously, the total is 510 mA (460 mA + 50 mA) extraon VMGTAVTTsupply.

4. What is the impact of this additional current and when does this happen?
This additional current happens only on the power-up and power-downramp. Once the GTP transceivers are powered up and running, then this has no impact.

5. What are the key things to keep in mind for the recommended power sequencing to avoid the additional current draw?
VMGTAVTT must be powered up last. VMGTAVCC and VCCINT mustbe powered up before VMGTAVTTbut they can be in any order. VMGTAVCCAUX has no recommended sequencing. These are the criterion that ensure the recommended sequencing is met and there is no current draw.

Revision History
08/22/2012 - Added the FAQ section
07/26/2012 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47852 7 Series FPGAs GTP Transceivers - Known Issues and Answer Record List N/A N/A
51456 Design Advisory Master Answer Record for Artix-7 FPGA N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
51192 Artix-7 FPGA Initial Engineering Sample (IES) - Known Issues Master Answer Record N/A N/A
AR# 51017
Date Created 07/26/2012
Last Updated 08/23/2012
Status Active
Type Design Advisory
Devices
  • Artix-7