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AR# 51063 14.1 Zynq-7000 - Why is QSPI programming not working when the feedback clock is used?

Description

When programming or operating a QSPI device with a clock frequency greater than FQSPICLK2 (see DS187), MIO[8] (qspi_sclk_fb_out) can only be floated or connected to a pull-up/pull-down resistor on the PCB, and Quad-SPI external loopback must be enabled.

Check that the MIO[8] pin is not connected to any additional resistive or capacitive loads other than what is stated in the Zynq TRM when using the QSPI with the Feedback Clock mode enabled.

Solution

To program QSPI reliably with a clock that is greater than FQSPICLK2:

  • Ensure that the MIO[8] (qspi_sclk_fb_out) is floated or connected to a pull-up/pull-down resistor on the PCB, and that the Quad-SPI external loopback is be enabled. MIO[8] must be free of any additional loading.

To program QSPI reliably with a QSPI Clock that is less than FQSPICLK2:

  • Ensure that the operating frequency (QSPI interface clock) is lower than FQSPICLK2 (see DS187).
  • Make sure QSPI external loopback is disabled (see qspi.LPBK_DLY_ADJ register in the Zynq TRM).
  • Disabling the feedback mode allows MIO[8] to be used with additional loading.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
52540 Zynq-7000 AP SoC - Frequently Asked Questions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
51248 Zynq-7000 - What QSPI Clock mode/speed is supported on the ZC702? N/A N/A
51235 Zynq-7000 - 14.1/14.2 Xilinx QSPI programming tools (SDK and iMPACT) supports external loopback capable designs N/A N/A

Actions

AR# 51063
Date Created 09/05/2012
Last Updated 10/24/2012
Status Active
Type Known Issues
Devices
  • Zynq-7000
Tools
  • EDK - 14.1
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