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AR# 51075

14.1 - Trace incorrect constraint used for FIFO WR_CLK RD_CLK

Description

I have a FIFO element in my design and specify the constraints as follows:

NET "RD_CLK" TNM_NET = "RD_CLK";
NET "WR_CLK" TNM_NET = "WR_CLK";
TIMESPEC "TS_WR_CLK" = PERIOD "WR_CLK" 245 MHZ;
TIMESPEC "TS_RD_CLK" = PERIOD "RD_CLK" TS_WR_CLK*1.5;

Inthe timing report, the source and destination clocks do not match with the clock specified in the constraint. Why is this happening?

Timing constraint: TS_RD_CLK = PERIOD TIMEGRP "RD_CLK" TS_WR_CLK * 1.5 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
50 paths analyzed, 46 endpoints analyzed, 19 failing endpoints
19 timing errors detected. (19 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 4.146ns.
--------------------------------------------------------------------------------
Slack (setup path): -0.713ns (requirement - (data path - clock path skew + uncertainty))
Source: flop_1 (FF)
Destination: design/U0/xst_fifo_generator/.../fifo18e1 (RAM)
Requirement: 1.361ns
Data Path Delay: 1.763ns (Levels of Logic = 0)
Clock Path Skew: -0.276ns (0.710 - 0.986)
Source Clock: wr_clk_i rising at 4.081ns
Destination Clock: wr_clk_i rising at 5.442ns
Clock Uncertainty: 0.035ns

Solution

In this case, the FIFO element is covered by both TS_WR_CLK and TS_RD_CLK, and TS_RD_CLK is taking precedence as it is placed after TS_WR_CLK in the UCF.

This issue has been resolved in ISE Design Suite 14.2.

AR# 51075
Date Created 11/14/2012
Last Updated 11/14/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 14.1