We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 51135

7 Series Integrated Block for PCI Express v1.6 - The core does not link up on Z77 (Ivy Bridge) platform


Version Found: v1.6
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

The 7 Series Integrated Block for PCI Express v1.6 core does not link up successfully on anIntel Z77 (Ivy Bridge) platform.


This is a known issue for the core implemented in Artix and Kintex devices due to an Intel errata .

To work around this issue, set TX_RXDETECT_REF to 3'b011 in "gt_wrapper.v". By default, this parameter is set to : 3'b100.

The Intel errata can be found at:

The errata item associated with this issue is BV56.

NOTE: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
09/18/2012 - Minor updates
08/17/2012 - Initial release

AR# 51135
Date Created 09/17/2012
Last Updated 03/06/2013
Status Active
Type Known Issues
  • ISE Design Suite - 14.2
  • Vivado - 2012.2
  • 7 Series Integrated Block for PCI Express (PCIe)