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AR# 5114

FPGA Express 3.3 - An "Abort at 59" occurs when parallel logic is coded


Keywords: FPGA, Express, Foundation, VHDL, Verilog, abort, 59, instantiate

Urgency: Standard

General Description:
An "Abort at 59" error is reported when I code parallel logic.


One cause of the Synopsys internal error "Abort at 59" has been code such as:

U1: BUFG port map (I => clk, O => clk_out);
clk_out <= clk;

This code will cause problems because of the multiple drivers for clk_out, but FPGA Express does not report a valid error message. This has been seen with versions of FPGA Express up to and including 3.4.

To work around this problem, remove one of the assignments and re-synthesize.
AR# 5114
Date Created 11/25/1998
Last Updated 08/11/2003
Status Archive
Type General Article