Zynq-7000All Programmable SoCZC702 Evaluation Kit Master UCF (Rev 1.0) lists the IOSTANDARD as LVDS for the USRCLK_P and USRCLK_N User Clock pins.
NETUSRCLK_PLOC = Y9 |IOSTANDARD=LVDS; # Bank 13 VCCOVADJ-IO_L12P_TI_MRCC_13
NETUSRCLK_NLOC = Y8 | IOSTANDARD=LVDS; #Bank 13 VCCO VADJ -IO_L12N_TI_MRCC_13
Using this UCF in the tools causes errors - what is the problem here?
LVDS is not a valid IOSTANDARD, the IOSTANDARD should instead read LVDS_25.
Zynq-7000 EPP ZC702 Evaluation Kit Master UCF (Rev 2.0) is now available with the correct IOSTANDARD listed for USRCLK_P and USRCLK_N:
NETUSRCLK_P LOC = Y9 |IOSTANDARD=LVDS_25; # Bank 13 VCCOVADJ-IO_L12P_TI_MRCC_13
NET USRCLK_N LOC = Y8| IOSTANDARD=LVDS_25; #Bank 13 VCCO VADJ -IO_L12N_TI_MRCC_13
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 47864 | Zynq-7000 AP SoC ZC702 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |