1.  Switch / Jumper Settings
   
     Default Switch and Jumper Settings for the VC707 are:
    
     Start from a known safe scenario by verifying the default switch and jumper settings.  You can then set switches / jumpers for your application.

 

a.   GPIO DIP Switch SW2 Default Settings:

2.  Board Power

Power-ON LEDs: Initial power testing is performed on the bench using the AC-to-DC power adapter provided in the VC707 Evaluation Kit.  The status of Power-ON LEDs is an indication of board health.

a.  Check the status of the following LEDs at Power-ON:

 

3.  Cable detection
 
     The VC707 uses a USB A-to-micro B cable plugged into the VC707 Digilent USB-to-JTAG module, U26.  A 2-mm JTAG header (J4) is also provided in parallel for access by Xilinx download cables such as Platform Cable USB II and Parallel Cable IV.

a.  USB A-to-micro-B cable
     i.  Is the cable visible in Device Manager?  If the 3 items highlighted in the figure below are visible in Device Manager, this confirms that your USB cable is operational and has been correctly identified.
       
50079-16.jpg
    ii.  Are cable drivers loaded correctly?  Drivers for this cable should be included in the iMPACT installation.  However, if problems are experienced with USB A-to-micro-B cable connection, a Digilent plug-in can be downloaded from the link below.
         For installation, please follow the guidelines in the document provided in the downloaded files: http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,768&Prod=DIGILENT-PLUGIN.     
         This plug-in requires Adept systems 2.4 or later for Windows and Adept systems 2.3.9 or later for Linux. Adept software is available from Digilent: http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2.  
   iii.  Check system properties and environment variables.  For information on environment variables, see (Xilinx Answer 11630).

   iv.   Is the USB port enabled?  User can reboot their computer to re-initialize their USB buses.
    v.   Is the latest version of Xilinx tools, supporting this kit, correctly installed?  (iMPACT or ChipScope Pro)  (For supported SW version information, please see Kit Product Page: http://www.xilinx.com/products/boards-and-kits/EK-V7-VC707-G.htm)
         If an issue is suspected with tools installation, please see Installation and Licensing Guide (make sure to use the most recent version of tools, and associated documentation, which supports the VC707)
    vi.  Is the Operating System (OS) being used Windows 7?  If so, see (Xilinx Answer 41442) and (Xilinx Answer 44397).
    
         If the above steps fail to enable you to connect, please open a WebCase to further debug the problem.    
         In the WebCase notes, please include all debug steps taken to date.

b.   Platform Cable USB II

      i.  Is the cable visible in Device Manager?
   

51233-20.jpg
     ii.  Are the cable drivers loaded correctly?  Drivers for this cable should be included in the iMPACT installation.  However, if problems are experienced with the Platform Cable USB II connection, please follow the uninstall and reinstall instructions in (Xilinx Answer 44397).

    iii.  Check system properties and environment variables.  For information on environment variables, see (Xilinx Answer 11630).

    iv.  Is the USB port enabled?  User can reboot their computer to re-initialize their USB buses.

     v.  Is the latest version of Xilinx tools, supporting this kit, correctly installed?  (iMPACT or ChipScope Pro)  (For supported SW version information, please see Kit Product Page: http://www.xilinx.com/products/boards-and-kits/EK-V7-VC707-G.htm)
         If an issue is suspected with tools installation, please see Installation and Licensing Guide (make sure to use the most recent version of tools, and associated documentation, which supports the VC707)

    vi.  Is the Operating System (OS) being used Windows 7?  If so, see (Xilinx Answer 41442) and (Xilinx Answer 44397).

         If the above steps fail to enable you to connect, please open a WebCase to further debug the problem.    
         In the WebCase notes, please include all debug steps taken to date.

c.   Parallel Cable IV

      i. Are the cable drivers loaded correctly?  For more information, see (Xilinx Answer 9984).
     ii. If you receive the following message in iMPACT: 'ERROR: Device Control LPT_WRITE_CMD_BUFFER Failed', see (Xilinx Answer 22293).

    iii. Note: Parallel Cable IV speed cannot be modified in iMPACT 13.x and 12.x, see (Xilinx Answer 41808) for more details.

    iv.  If you cannot establish a connection with the Parallel Cable IV, see (Xilinx Answer 15742).

        If the above steps fail to enable you to connect, please open a WebCase to further debug the problem.
        In the WebCase notes, please include all debug steps taken to date.

4.  JTAG Initialization

     The status of the board JTAG chain is checked using Xilinx Tools (iMPACT or ChipScope Pro).  To check to see that the JTAG chain is initialized correctly, follow this JTAG initialization Test Case:

     a. Remove any FMC cards from VC707
     b. Set the mode bits of switch SW11 for JTAG mode (101)
     c. Power up VC707 on the bench (not in a PC chassis)
     d. Connect the Digilent USB A-to-micro-B cable to the VC707 (through the Digilent onboard USB-to-JTAG configuration logic module - U26)
     e. Check Digilent device shows up in Device Manager
     f. Ensure Xilinx tools (ISE 13.4 or later - preferably the latest version which supports VC707) are correctly installed
     g. Launch iMPACT - is the cable identified correctly? 
          i.  If not, see section 3. Cable detection above.
          ii.  If yes, but iMPACT did not discover and display the JTAG chain, slow down the cable speed (Output > Cable Setup)
          iii.  If yes, but iMPACT did not discover and display the JTAG chain, and slowing the cable speed does not resolve the issue, see the following (assumes Digilent USB A-to-micro B cable is plugged into USB-to-JTAG configuration logic module U26):
       
51233-3.jpg
       
If the above steps fail to enable you to initialize the JTAG chain, please disconnect the Digilent USB A-to-micro-B cable from the board and PC.  Connect the Platform Cable USB to header J4, and connect to your PC. Ensure Xilinx tools (preferably the latest version of tools that support the VC707) are correctly installed.  Launch iMPACT - is the cable identified correctly?
         
If the above steps fail to enable you to connect, please open a WebCase to further debug the problem.     
In the WebCase notes, please include all debug steps taken to date. 

5.  JTAG Configuration

     If JTAG chain initializes OK, but JTAG configuration fails, check the following:

a.  Verify the mode switch settings for JTAG configuration mode:

          S11-3     (M2)     1
          S11-4     (M1)     0
          S11-5     (M0)     1

b.  In iMPACT, select a lower cable frequency (Output > Cable Setup) and re-attempt configuration.
c.  In iMPACT, run the Chain Integrity test by selecting Debug > Chain Integrity Test.  iMPACT will assist in the debugging of this scenario by providing insight into where the failing connection in the chain could be.
d.  Pulse the PROG push button on the KC705 (SW14).  Pulsing PROG will clear out any problems caused by power up ramp rate issues to the FPGA.
e.  Read back the FPGA Status Register in iMPACT (Debug > Read Status Register).  The information extracted from the Status Register can help determine the stage of configuration and where a failure has occurred. For more details, see (Xilinx Answer 24024).
f.   Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center. The Configuration Solution Center is available to address all questions related to Configuration.

     If the above steps fail to enable JTAG configuration, please open a WebCase to further debug the problem.    
     In the WebCase notes, please include all debug steps taken to date.

 

6.  Master BPI Configuration

     The iMPACT software tool can be used to indirectly program the Linear BPI Flash memory (U3) on the VC707.  U3 provides 128 MB of nonvolatile storage that can be used for configuration or software storage. 

a.  To confirm the BPI interface on the board is working using a known working example design, download and run the VC707 Restoring Flash Contents Design Files, whichever version is appropriate for your silicon and software version.
     It is recommended to always use the latest version of software which supports the VC707, and the associated version of the VC707 Restoring Flash Contents Design Files.
     Follow the associated PDF.  All are available from the VC707 Example Designs page.
  

51233-21.jpg
     To identify the silicon version of your kit (C or CES), see (Xilinx Answer 37579).
b.  Read the VC707  Restoring Flash Contents design document: VC707 Restoring Flash Contents PDF: xtp145.pdf; VC707 Restoring Flash Contents Vivado PDF: xtp208.pdf and follow the instructions therein.

     If U3 (BPI flash) on the VC707 contains an image (the as-shipped BIST image or a user-programmed image) and the Virtex-7 FPGA does not configure as expected from the BPI flash, then the following points should be checked:

c.  If the .mcs file is correctly loaded, you will see the FPGA and the FLASH device in the JTAG chain, as shown here:
   
51233-19.jpg
     If you do not see the FLASH device attached to the xc7vx485t, as shown, see the iMPACT Help section of ISE Help.
d.  Verify the mode switch settings for Master BPI configuration:

          S11-3     (M2)     0
          S11-4     (M1)     1
          S11-5     (M0)     0

e. In iMPACT, select a lower cable frequency and re-attempt configuration.
f.  Pulse the PROG push button on the VC707 (SW9), to attempt to reload the FPGA with the configuration image.
g. Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center. The Configuration Solution Center is available to address all questions related to Configuration.

     If the above steps fail to enable BPI configuration, please open a WebCase to further debug the problem.    
     In the WebCase notes, please include all debug steps taken to date. 

7.  XADC

a.  Verify XADC jumper settings - see Section 1. Switch / Jumper Settings, part d, above.
b.  Ensure Xilinx tools (latest version which support VC707) are correctly installed on your machine.
c.  To test the XADC interface on the VC707, use a known working reference design.  If you have access to the AMS101 Evaluation Card (shown below) with the VC707, download and run the Virtex-7 FPGA VC707 Evaluation Kit AMS Targeted Reference Design (latest version) to check the XADC functionality.
    

50079-23.jpg
     Please ensure you have the correct version of Vivado Design Suite installed to run this TRD.  It is recommended to always use the latest version of software, TRD, and associated documentation (7 Series FPGA AMS Targeted Reference Design User Guide).
     You can download this Targeted Reference Design, as well as the AMS Evaluator Installer and Documentation for this TRD, from the VC707 Documentation page.
d.  Details on XADC operation can be found in UG480 and UG772.  (Be sure to use the most recent version of the document.)

     If the above steps fail to resolve the XADC issue, please open a WebCase to further debug the problem.
     In the WebCase notes, please include all debug steps taken to date.

8.  PCIe

     If the VC707 configures correctly, however the PCIe interface does not operate as expected, check the following:

a.  Do NOT plug a PC ATX power supply 6-pin connector into J18 on the VC707 board. The ATX 6-pin connector has a different pinout than J18.  Connecting an ATX 6-pin connector into J18 will damage the VC707 board and void the board warranty.
     To install and power the board correctly, follow the instructions given in UG885 VC707 Evaluation Board User Guide - Appendix D - Board Setup.
b.  Check J49, the lane width, is set correctly for your application.
c.  See (Xilinx Answer 40469) - 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions affecting 7 series, including Virtex-7.
d.  Download and run the VC707 PCIe Example Design, whichever version is appropriate for your silicon and software version.  It is recommended to always use the latest version of software, and associated version of the VC707 PCIe Example Design.
     Follow the associated PDF.  All are available from the VC707 Example Designs page.

  

51233-10.jpg

     To identify the silicon version of your kit (C or CES), see (Xilinx Answer 37579).
e.  Read the VC707 PCIe Example Design document: VC707 PCIe PDF: xtp144.pdf; VC707 PCIe Vivado PDF: xtp207.pdf
f.   Review (Xilinx Answer 34536) - Xilinx Solution Center for PCI Express.  The Solution Center for PCI Express is available to address all questions related to the Xilinx solutions for PCI Express.

     If the above steps fail to resolve the PCIe issue, please open a WebCase to further debug the problem.
     In the WebCase notes, please include all debug steps taken to date.

9. IBERT

      Note: Running IBERT requires the installation of ChipScope.  A device-locked license for this software is provided with the Virtex-7 FPGA VC707 Evaluation Kit.
      If the VC707 configures correctly, however IBERT does not operate as expected, check the following:

a.   If using MGT loopback, ensure you have the correct equipment, including SMA cables, SMA Quick connects and Connect Optical Loopback Adapter:
    

50079-21.jpg
50079-20.jpg
50079-22.jpg
      More information can be found in the VC707 GTX IBERT PDF or VC707 GTX IBERT VIVADO PDF, from the VC707 Example Designs page.
b.   Download and run the VC707 GTX IBERT Example Design, whichever version is appropriate for your silicon and software version.  It is recommended to always use the latest version of software, and associated version of the VC707 GTX IBERT Example Design.
      Follow the associated PDF.  All are available from the VC707 Example Designs page.

   

51233-11.jpg

      To identify the silicon version of your kit (C or CES), please see (Xilinx Answer 37579).

c.   Read the VC707 GTX IBERT Example Design document: VC707 GTX IBERT PDF: xtp141.pdf; VC707 GTX IBERT Vivado PDF: xtp210.pdf
d.   Review (Xilinx Answer 45201) - Xilinx ChipScope Solution Center - IBERT Design Assistant.  The ChipScope Solution Center is available to address all questions related to ChipScope.

      If the above steps fail to resolve the IBERT issue, please open a WebCase to further debug the problem.
      In the WebCase notes, please include all debug steps taken to date.

10. Multiboot

     If VC707 initial configuration was successful, however Multiboot is not working as expected, check the following:

a.  Verify steps taken to program VC707 with Multiboot bitstream in iMPACT (if using a custom bitstream); refer to UG470.
b.  Download and run the VC707 Multiboot Example Design, whichever version is appropriate for your silicon and software version.  It is recommended to always use the latest version of software, and associated version of the VC707 Multiboot Example Design.

     Follow the associated PDF.  All are available from the VC707 Example Designs page.

  

51233-12.jpg

     To identify the silicon version of your kit (C or CES), please see (Xilinx Answer 37579).
c.  Read the VC707 Multiboot Example Design document: VC707 Multiboot PDF: xtp142.pdf ; VC707 Multiboot Vivado PDF: xtp219.pdf

     If the above steps fail to resolve the Multiboot issue, please open a WebCase to further debug the problem.

     In the WebCase notes, please include all debug steps taken to date.

11. DDR3

      The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module (SODIMM).  If a problem is suspected with DDR3 / MIG, check the following:

a.   Ensure DDR3 SODIMM module is inserted correctly.
b.   Download and run the VC707 MIG Example Design, whichever version is appropriate for your silicon and software version.  It is recommended to always use the latest version of software, and associated version of the VC707 MIG Example Design.
      Follow the associated PDF.  All are available from the VC707 Example Design page.
   
51233-13.jpg
      To identify the silicon version of your kit (C or CES), please see (Xilinx Answer 37579).
c.   Read the VC707 MIG Example Design document: VC707 MIG PDF: xtp143.pdf; VC707 MIG Vivado PDF: xtp206.pdf
d.   Review (Xilinx Answer 34243) - Xilinx MIG Solution Center.  The Memory Interface Generator (MIG) Solution Center is available to address all questions related to MIG.

      If the above steps fail to resolve the DDR3 issue, please open a WebCase to further debug the problem.
      In the WebCase notes, please include all debug steps taken to date.



12. Interface Tests

     (Xilinx Answer 54161) - Virtex-7 FPGA VC707 Evaluation Kit - Interface Test Designs can be run to ensure that the interfaces on the VC707 are working correctly. This Answer Record forms part of (Xilinx Answer 43748) - Xilinx Boards and Kits Debug Assistant.
     If the above tests fail to resolve the issue, please open a WebCase to further debug the problem.
     In the WebCase notes, please include all debug steps taken to date.



13. Known Issues for VC707
 
All Known Issues for the Virtex-7 FPGA VC707 Evaluation Kit are listed in (Xilinx Answer 45382) - Virtex-7 FPGA VC707 Evaluation Kit - Known Issues and Release Notes Master Answer Record. If the issue you are faced with is not listed in the Known Issues and Release Notes Master Answer Record, and the steps above fail to resolve the issue, please open a WebCase to further debug the problem. In the WebCase notes, please include all debug steps taken to date.