Vivado Synthesis today does not support the FSM Safe Implementation feature.
What would be the best practice to account for invalid states of a state machine? Will Safe Implementation be available in future Vivado tool releases?
The Safe Implementation feature is scheduled to be added to Vivado Synthesis tool in version 2012.4. It is recommended that you use this synthesis option when it isavailable. Using this attribute will allow you to redirect a state machine to a predefined "safe" state when an invalid or unreachable state is encountered.
Until Safe Implementation is ready, users can add a default state to a finite state machine case statement with -fsm_extraction set to "NO" in order to guarantee that Vivado Synthesis uses the default statement. Vivado Synthesis will use the default state and redirect invalid or unreachable states using this default clause statement. If -fsm_extraction is set to Yes, care should be taken to make sure that the FSM has reachable states. Optimization of the default statement can occur for unreachable states.