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AR# 5124

F1.5i Simulator, Virtex: Cannot simulate CLKDLL component in a Timing Simulation.

Description

Keywords: 1.5i, Foundation, Simulator, functional, logic, clkdll, virtex

Urgency: Standard

General Description:
Simulating CLKDLL in Foundation Simulator 1.5i does not produce any
clock frequency, just a constant value.

Solution

This problem has been corrected for all outputs of the CLKDLL except
the DIVIDE output. This will be resolved in a future software release.

F1.5i Service Pack 2 fixes the other outputs and is available at:

http://support.xilinx.com/support/techsup/sw_updates/

Note: This software update only enable timing simulation of the CLKDLL.
Functional simulation will not work.
AR# 5124
Date Created 12/01/1998
Last Updated 03/07/2002
Status Archive
Type General Article