UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 51256

EDK 14.2 - INSTANCE: axi_interconnect_2, PORT: S_AXI_AWUSER, CONNECTOR: axi_interconnect_2_S_AWUSER - 4 bit-width connector assigned to 2 bit-width port

Description

Why do I receive this error when running DRCs on my EDK design?

ERROR:EDK:4073 - INSTANCE: axi_interconnect_2, PORT: S_AXI_AWUSER, CONNECTOR: axi_interconnect_2_S_AWUSER - 4 bit-width connector assigned to 2 bit-width port ....

Solution

This error happens when there is a mismatch in port sizes between connected IP.

In this case specifically, it turns out that the AXI interconnect has settings for the AWUSER/ARUSER signals to define their bit widths. 

By default, this is set to auto.

Currently (as of 14.2), setting this to AUTO does not seem to resolve mis-matches.

 

To work around the issue, right click on the axi_interconnect that is failing, and select "Config IP". 

Under the General tab, change the Read/write Address User Signal Width to match the expected value in the system. 

See below:

51256-1

 

AR# 51256
Date Created 10/03/2012
Last Updated 03/23/2015
Status Active
Type General Article
Tools
  • EDK - 14.2
  • EDK - 14.1
IP
  • AXI Interconnect