Why do I receive this error when running DRCs on my EDK design?
This error happens when there is a mismatch in port sizes between connected IP.
In this case specifically, it turns out that the AXI interconnect has settings for the AWUSER/ARUSER signals to define their bit widths.
By default, this is set to auto.
Currently (as of 14.2), setting this to AUTO does not seem to resolve mis-matches.
To work around the issue, right click on the axi_interconnect that is failing, and select "Config IP".
Under the General tab, change the Read/write Address User Signal Width to match the expected value in the system.