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AR# 51276

What does the warning: Warning-[TFIPC] Too few instance port connections mean when I am simulating my MIG 7 series design?

Description

When trying to simulate the example design generated by CoreGen for a MIG DDR3 design with VCS I receive the following warning:

Warning-[TFIPC] Too few instance port connections
  The following instance has fewer port connections than the module definition
  "../../user_design/rtl/phy/ddr_byte_group_io.v", 204: ISERDESE2
  #(.DATA_RATE(ISERDES_DQ_DATA_RATE), .DATA_WIDTH(ISERDES_DQ_DATA_WIDTH),
  .DYN_CLKDIV_INV_EN(ISERD ...

Can I safely ignore this warning?

Solution

The below is from the ISERDES2 module from the Unisims directory:
 
(line 78)
      output O;
      output Q1;
      output Q2;
      output Q3;
      output Q4;
      output Q5;
      output Q6;
      output Q7;
      output Q8;
      output SHIFTOUT1;
      output SHIFTOUT2;
 
      input BITSLIP;
      input CE1;
      input CE2;
      input CLK;
      input CLKB;
      input CLKDIV;
      input CLKDIVP;
      input D;
      input DDLY;
      input DYNCLKDIVSEL;
      input DYNCLKSEL;
      input OCLK;
      input OCLKB;
      input OFB;
      input RST;
      input SHIFTIN1;
      input SHIFTIN2;
 
The below is from the ddr_byte_group_io.v file, line 204:
 
             .O                          (),
             .Q1                         (iserdes_dout[4*i + 3]),
             .Q2                         (iserdes_dout[4*i + 2]),
             .Q3                         (iserdes_dout[4*i + 1]),
             .Q4                         (iserdes_dout[4*i + 0]),
             .Q5                         (),
             .Q6                         (),
             .SHIFTOUT1                  (),
             .SHIFTOUT2                  (),
 
             .BITSLIP                    (1'b0),
             .CE1                        (1'b1),
             .CE2                        (1'b1),
             .CLK                        (iserdes_clk_d),
             .CLKB                       (!iserdes_clk_d),
             .CLKDIVP                    (iserdes_clkdiv),
             .CLKDIV                     (),
             .DDLY                       (data_in_dly[i]),
             .D                          (data_in[i]),
                                         // dedicated Route to iob for debugging
                                         // or as needed, select with IOBDELAY
             .DYNCLKDIVSEL               (1'b0),
             .DYNCLKSEL                  (1'b0),
 
 Notice that in this definition, Q7, Q8, OCLK, OCLKB, OFB and reset have not been defined in the module, resulting in the warning below:
 
 Warning-[TFIPC] Too few instance port connections
      The following instance has fewer port connections than the module definition
      "../../user_design/rtl/phy/ddr_byte_group_io.v", 204: ISERDESE2
      #(.DATA_RATE(ISERDES_DQ_DATA_RATE),
 .DATA_WIDTH(ISERDES_DQ_DATA_WIDTH),
      .DYN_CLKDIV_INV_EN(ISERD ...
 
What is happening here is that Xilinx FPGA devices offer components that can feature different modes of operation. 

Depending on the mode of operation, all, or a subset of the ports are used to achieve functionality.  

The HDL Libraries Guide for any specific part defines which values are assigned to ports for different modes of operation.

In some instances, ports may be left open, or left unconnected. 

In this case the values are unconnected and it is safe to ignore this warning.
 
AR# 51276
Date Created 08/13/2012
Last Updated 12/10/2014
Status Active
Type General Article
Devices
  • FPGA Device Families
IP
  • MIG 7 Series