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AR# 5128

LogiCORE PCI - When is the S_WRDN signal valid?

Description

General Description:

The PCI32 User Guide states that S_WRDN is valid during ADDR_VLD and held through the entire transaction. Is this correct?

Solution

S_WRDN is sampled on the next clock after the assertion of ADDR_VLD. It indicates a WRITE when asserted High and a READ when asserted Low.

ADDR_VLD is asserted only during the address phase, while S_WRDN remains at a stable value until the end of the transaction.

AR# 5128
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article